CS496122-CQZ Cirrus Logic Inc, CS496122-CQZ Datasheet - Page 20

IC DSP 32BIT 16CH SER IO 144LQFP

CS496122-CQZ

Manufacturer Part Number
CS496122-CQZ
Description
IC DSP 32BIT 16CH SER IO 144LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Processorr
Datasheets

Specifications of CS496122-CQZ

Applications
Audio routing, processing
Mounting Type
Surface Mount
Package / Case
144-LQFP
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1022 - MODULE COBRANET 4961 CM2 MT598-1007 - EVAL BOARD CS496122 COBRANET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1073

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Part Number:
CS496122-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
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Part Number:
CS496122-CQZ
Manufacturer:
CIRRUS
Quantity:
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Part Number:
CS496122-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
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CobraNet Hardware User’s Manual
Digital Audio Interface
6.1
20
Digital Audio Interface Timing
Although data is always transmitted and received with a 32-bit resolution by the
synchronous serial ports, the resolution of the data transferred to/from the Ethernet may
be less. Incoming audio data is truncated to the selected resolution. Unused least
significant bits on outgoing data is zero filled.
An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows
a MCLK_OUT edge by 0.0 to 10.0ns.
Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to
the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the
edge of DAO1_SCLK.
DAO1_DATAx
DAI1_DATAx
DAO1_SCLK
DAO1_SCLK
MCLK_OUT
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1
Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or
FS1
the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends
on power up timing.
Figure 7. Serial Port Data Timing Overview
©
Copyright 2005 Cirrus Logic, Inc.
0 – 12ns
≥5ns
0 – 10ns
0 – 5ns
≥0ns
DS651UM23
Version 2.3

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