AD9726 Analog Devices, AD9726 Datasheet - Page 18

• Manufacturer Part Number: AD9726
• Manufacturer: Analog Devices

Specifications of AD9726

• Resolution (bits): 16bit
• Dac Update Rate: 400MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9726
The 50 Ω termination resistor should be placed as close as pos-
sible to the input pins, and controlled impedance PCB traces
should be used.
Good ac performance can be expected from either the active or
passive DAC clock drive circuit. However, in a passive circuit,
the output slew rate is dependent on the frequency of the input;
whereas an active circuit provides consistently high output slew
rates over a wide range of input frequencies.
DATA SYNCHRONIZATION CIRCUITRY
The high performance of the AD9726 requires maintaining
synchronization between the incoming bits and the DAC clock
used to sample and convert the data. Despite the inherent dif-
ficulty in specifying the phase relationship of the DAC clock
and the LVDS data clock input and the challenge presented by
the high operating speed of the interface, the AD9726 contains
real-time logic to automatically monitor and align the data bus
with the DAC clock.
Whether in SDR or DDR mode, input data is always provided
at the same rate. Furthermore, the rate of incoming data always
equals the frequency period of the DAC clock. The data rate and
the DAC clock must also be frequency locked. To accomplish this,
the primary purpose of the data clock output is to provide a
time base for data that is derived directly from the DAC clock.
The function of the data clock input is to latch incoming data
into the sync block. From there, it is the function of the
synchronization logic to position the data with respect to the
DAC clock for optimal ac performance.
Individual data bits must maintain close alignment with one
another so that PCB traces have matched delays across the
width of the 16-bit bus. In addition, a fixed setup and hold
timing relationship between the data clock input and the data
bus is required.
However, because of the sync logic, the phase relationship between
the data bus and the DAC clock is internally optimized.
Furthermore, if the phase between the data bus and the DAC
clock drifts over time or temperature, the sync logic automat-
ically updates and adjusts for it. After synchronization is
reached, the phase between the data bus and the DAC clock can
vary by a full cycle without loss or corruption of data.
More detailed explanations of sync operation and optional
programmable modes are presented in the Sync Logic
Operation and Programming section, which also includes an
explanation of how to use the sync logic without the SPI.
Data Synchronization Circuitry Bypass
Due to internal design limitations, the data synchronization
circuitry does not assure a fixed or predictable pipeline delay
between the data input and the analog output after power-up.
For designs where multichip synchronization or fixed pipeline
delay is important, the AD9726 can be configured to bypass the
resynchronization circuitry and assure a fixed pipeline delay of
four DAC clock cycles. In this mode, the data is sampled into
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the DAC using the DAC clock (CLK±) and following the timing
presented in Figure 4, Figure 5, and Table 4.
The data synchronization circuitry bypass is enabled by writing
0x40 to Address 0x16. The AD9726 should also be configured
in single data rate mode by writing 0x80 to Address 0x02. In this
mode, the sync logic is bypassed, making its configurations and
status reporting irrelevant.
ANALOG OUTPUT
The AD9726 is based around a high dynamic range CMOS
core. The analog output consists of differential current sources,
each capable of up to 20 mA full scale. Discrete output devices
are PMOS and capable of sourcing current into an output
termination within a compliance voltage range of ±1 V.
In a typical application, both outputs drive discrete resistors-to-
analog ground. From there, especially for higher frequency
outputs, they feed the center-tap secondary of a 1:1 RF trans-
former. A differential-to-single-ended conversion is accomplished
that provides added gain and cancellation of even ordered
harmonics.
For maximum output power, resistor values can be increased to
50 Ω to provide up to 0 dBm into a 50 Ω load without loss of
performance for most transformers.
As an alternative, an active output stage can be used in the
classic instrumentation amplifier configuration. Here, each
DAC output feeds the noninverting input of one of the Analog
Devices, Inc., high speed transimpedance op amps.
IOUTA
IOUTB
IOUTA
IOUTB
NOTES
1. USE RF AND RG TO SET GAIN
Figure 21. Transformer Output Circuit
AND LIMIT BANDWIDTH
Figure 22. Op Amp Output Circuit
25Ω
25Ω
50Ω
50Ω
R
R
GA
GB
R
R
FA
FB
–3dBm