AD5452 Analog Devices, AD5452 Datasheet - Page 24
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AD5452
Manufacturer Part Number
AD5452
Description
12-Bit High Bandwidth Multiplying DACs with Serial Interface
Manufacturer
Analog Devices
Datasheet
1.AD5453.pdf
(32 pages)
Specifications of AD5452
Resolution (bits)
12bit
Dac Update Rate
2.7MSPS
Dac Settling Time
160ns
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Ser,SPI
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AD5450/AD5451/AD5452/AD5453
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 62 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
PIC16C6x/PIC16C7x-to-
AD5450/AD5451/AD545
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
In this example, I/O Port RA1 is used to provide a SYNC
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 63 shows the connection diagram.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
PIC16C6x/PIC16C7x*
MICROWIRE*
Figure 63. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
Figure 62. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interfac
SCK/RC3
SDI/RC4
RA1
SO
SK
CS
2/AD5453 Interface
AD5452/AD5453*
AD5450/AD5451/
AD5452/AD5453*
SCLK
SDIN
SYNC
AD5450/AD5451/
SCLK
SDIN
SYNC
signal
e
Rev. E | Page 24 of 32
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
an
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point
The star gro
to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close to the pack
as possible, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to intern
switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast switching signa
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on oppos
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
It i
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as c
the device as possible.
d confined to certain areas of the board. If the DAC is in a
s good practice to employ compact, minimum lead length
und point should be established as close as possible
REF
and R
FB
should also be
al logic
lose to
only.
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age
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