AD5428 Analog Devices, AD5428 Datasheet - Page 18

• Manufacturer Part Number: AD5428
• Description: Dual 8-Bit, High Bandwidth Multiplying DACs with Parallel Interface
• Manufacturer: Analog Devices

Specifications of AD5428

• Resolution (bits): 8bit
• Dac Update Rate: 21.3MSPS
• Dac Settling Time: 30ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD5428/AD5440/AD5447
Bipolar Operation
In some applications, it may be necessary to generate full 4-quad-
rant multiplying operation or a bipolar output swing. This can
easily be accomplished by using another external amplifier and
some external resistors, as shown in Figure 39. In this circuit, the
second amplifier, A2, provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages are
created as the input data (D) is incremented from Code 0 (V
−V
When connected in bipolar mode, the output voltage is given by
where:
D is the fractional representation of the digital word loaded to
the DAC.
n is the number of bits.
When V
multiplication. Table 8 shows the relationship between digital
code and the expected output voltage for bipolar operation
using the 8-bit AD5428.
D = 0 to 255 (AD5428)
V
REF
OUT
= 0 to 1023 (AD5440)
= 0 to 4095 (AD5447)
) to midscale (V
IN
=
is an ac signal, the circuit performs 4-quadrant
(
V
REF
INPUTS
1
2
3
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.
C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
DATA
ADJUST R3 FOR V
×
D
DAC A/B
OUT
2 /
DGND
DB11
DB7
DB9
DB0
R/W
V
CS
DD
n
= 0 V) to full scale (V
−1
)
OUT
−
AD5428/AD5440/AD5447
V
B = 0V WITH CODE 10000000 IN DAC B LATCH.
REF
POWER-ON
CONTROL
BUFFER
RESET
INPUT
LOGIC
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
OUT
= +V
LATCH
LATCH
REF
).
OUT
Rev. C | Page 18 of 32
V
V
=
REF
REF
(±10V)
(±10V)
A
B
V
8-/10-/12-BIT
8-/10-/12-BIT
R-2R DAC A
R-2R DAC B
V
IN
IN
A
B
R1
R3
1
1
Table 8. Bipolar Code
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Stability
In the I-to-V configuration, the I
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closed-
loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with R
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
R
R
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
FB
I
AGND
I
OUT
OUT
R
R
A for stability, as shown in Figure 38 and Figure 39. Too
FB
FB
A
B
A
B
R2
R4
1
1
AGND
AGND
C1
C2
3
3
A1
A3
20kΩ
10kΩ
10kΩ
20kΩ
R10
R6
R7
R9
2
2
2
2
Analog Output (V)
+V
0
–V
–V
AGND
AGND
REF
REF
REF
OUT
5kΩ
R11
R12
5kΩ
(127/128)
(128/128)
(127/128)
20kΩ
20kΩ
A2
R5
A4
of the DAC and the inverting
R8
V
V
OUT
OUT
A
B
Data Sheet