AD5392 Analog Devices, AD5392 Datasheet - Page 28

• Manufacturer Part Number: AD5392
• Description: 8-Channel 14-Bit Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5392

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5390/AD5391/AD5392
3-BYTE MODE
The 3-byte mode lets the user update more than one channel in
a write sequence without having to write the device address byte
each time. The device address byte is required only once and
subsequent channel updates require the pointer byte and the
data bytes. In 3-byte mode, the user begins with an address byte
(R/ W = 0) after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte; this addresses the specific channel in the
DAC to be addressed and is also acknowledged by the DAC.
Address Bits A3 to A0 address all channels on the
AD5390/AD5391. Address Bits A2 to A0 address all channels
SCL
SDA
SCL
SDA
SDA
SDA
SCL
SCL
CONDITION
MASTER
START
BY
REG1
MSB
REG1
1
0
REG0
0
REG0
POINTER BYTE FOR CHANNEL NEXT CHANNEL
0
MSB
MOST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
1
MSB
0
ADDRESS BYTE
0
0
1
A3
AD1
A2
AD0
Figure 35. 3-Byte Mode I
A1
DATA FOR CHANNEL NEXT CHANNEL
DATA FOR CHANNEL N
LSB
R/W
LSB
A0
CONVERTER
CONVERTER
Rev. C | Page 28 of 40
CONVERTER
CONVERTER
ACK
ACK
BY
BY
ACK
ACK
BY
BY
MSB
MSB
A/B
MSB
2
C Write Operation
on the AD5392. Address Bit A3 is a zero on the AD5392. This is
then followed by the two data bytes. REG1 and REG0 determine
the register to be updated.
If a STOP condition is not sent following the data bytes,
another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode requires only three
bytes to be sent to update any channel once the device has
been initially addressed and reduces the software overhead in
updating the AD539x channels. A STOP condition at any time
exits this mode. Figure 35 shows a typical configuration.
0
POINTER BYTE FOR CHANNEL N
LEAST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
0
0
A3
A2
A1
LSB
A0
CONVERTER
CONVERTER
CONVERTER
LSB
ACK
ACK
ACK
BY
BY
BY
CONDITION
MASTER
STOP
BY