AD9773 Analog Devices, AD9773 Datasheet - Page 50
AD9773
Manufacturer Part Number
AD9773
Description
Manufacturer
Analog Devices
Datasheet
1.AD9773.pdf
(60 pages)
Specifications of AD9773
Resolution (bits)
12bit
Dac Update Rate
400MSPS
Dac Settling Time
11ns
Max Pos Supply (v)
+3.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Par
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9773BSV
Manufacturer:
AD
Quantity:
1 831
Company:
Part Number:
AD9773BSV
Manufacturer:
ADI
Quantity:
329
Company:
Part Number:
AD9773BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9773BSVZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9773BSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9773
Figure 103. Test Configuration for AD9773 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
Figure 104. Test Configuration for AD9773 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
ONEPORTCLK = Interleaved Input Data Rate = 2x Signal Generator Frequency/Interpolation Rate
NOTES
1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25
NOTES
1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT
PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. FOR MORE INFORMATION, SEE THE
TWO-PORT DATA INPUT MODE SECTION.
INPUT CLOCK
INPUT CLOCK
JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL OFF
JUMPER CONFIGURATION FOR ONE-PORT MODE, PLL OFF
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
AWG2021
AWG2021
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
DG2020
DG2020
OR
OR
DATACLK = Signal Generator Frequency/Interpolation Rate
SOLDERED/IN
SOLDERED/IN
LECROY
PULSE
GENERATOR
LECROY
PULSE
GENERATOR
×
×
×
×
×
×
×
×
×
×
40-PIN RIBBON CABLE
UNSOLDERED/OUT
UNSOLDERED/OUT
Rev. D | Page 50 of 60
TRIG
TRIG
INP
INP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
DATACLK
ONEPORTCLK
DAC1, DB11–DB0
DAC2, DB11–DB0
DAC1, DB11–DB0
DAC2, DB11–DB0
SIGNAL GENERATOR
SIGNAL GENERATOR
CLK+/CLK–
CLK+/CLK–
AD9773
AD9773