AD5532HS Analog Devices, AD5532HS Datasheet - Page 8

• Manufacturer Part Number: AD5532HS
• Description: 32-Channel 14-Bit bipolar DAC with High Speed 3-Wire Serial Interface
• Manufacturer: Analog Devices

Specifications of AD5532HS

• Resolution (bits): 14bit
• Dac Update Rate: 1.1MSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +12V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5532HS
FUNCTIONAL DESCRIPTION
The AD5532HS consists of 32 DACs in a single package. A
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (V
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the 5-bit DAC address
and 14-bit DAC data have been loaded the selected DAC
converts the code.
On power-on, all the DACs are loaded with zeros.
Digital-to-Analog Section
The architecture of each DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the REF_IN pin provides the reference voltage for the cor-
responding DAC. Since the input coding to the DAC is straight
binary, the ideal DAC output voltage is given by:
where D = decimal equivalent of the binary code that is loaded
to the DAC register i.e., 0–16,383.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the
0 V–2.5 V output of the DAC to a wider range. This is done by
gaining up the DAC output by two and offsetting the voltage
by the voltage on OFFS_IN pin.
V
V
Table I shows how the output range of V
voltage supplied by the user.
V
(V)
0
2.5
V
V
DAC
OFFS_IN
OFFS_IN
OUT
OUT
is the output of the DAC.
is limited only by the headroom of the output amplifiers.
must be within maximum ratings.
is the voltage at the OFFS_IN pin.
Table I. Sample Output Voltage Ranges
V
OUT
V
DAC
=
V
(V)
0 to 2.5
0 to 2.5
(
DAC
2
=
×
V
V
DAC
REF
2
_
) –
14
IN
V
×
OFFS IN
OUT
D
OUT
0–V
_
relates to the offset
OUT
V
(V)
0 to 5
–2.5 to +2.5
31).
OUT
–8–
Reset Function
The reset function on the AD5532HS can be used to reset all
nodes on the device to their power-on-reset condition. All the
DACs are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins as follows:
SYNC: This pin is the Frame Synchronization pin for the serial
interface.
SCLK: This pin is the Serial Clock Input. It operates at clock
speeds up to 30 MHz.
D
the falling edge of SCLK.
To update a single DAC channel a 19-bit data-word is written
into the AD5532HS. See Table II.
MSB
A4–A0 Bits
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
DB13–DB0 Bits
These are used to write a 14-bit word into the addressed
DAC register.
Figure 1 shows the timing diagram for a serial write to the
AD5532HS. The serial interface works with both a continuous and
a noncontinuous serial clock. The first falling edge of SYNC resets
a counter that counts the number of serial clocks to ensure
the correct number of bits are shifted in and out of the serial
shift registers. Any further edges on SYNC are ignored until the
correct number of bits are shifted in or out. Once 19 bits have
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place, the counter must be reset by the
falling edge of SYNC. The user must allow 280 ns (min)
between successive writes (refer to Timing Specifications).
A4
IN
: This pin is the Serial Data Input. Data must be valid on
A3
Table II. Serial Data Format
A2
A1
A0
DB13–DB0
REV. 0
LSB