AD5307 Analog Devices, AD5307 Datasheet - Page 21

• Manufacturer Part Number: AD5307
• Manufacturer: Analog Devices

Specifications of AD5307

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

OPTO-ISOLATED INTERFACE FOR
PROCESS-CONTROL APPLICATIONS
The AD5307/AD5317/AD5327 each have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process-control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5307/AD5317/AD5327 from the controller. This can easily
be achieved by using opto-isolators capable of providing isolation
in excess of 3 kV. The actual data rate achieved can be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5307/AD5317/AD5327 makes them ideally suited for
use in opto-isolated applications. Figure 43 shows an opto-isolated
interface to the AD5307/AD5317/AD5327 where DIN, SCLK,
and SYNC are driven from optocouplers. The power supply to
the part should also be isolated. This is done by using a trans-
former. On the DAC side of the transformer, a 5 V regulator
provides the 5 V supply required for the AD5307/AD5317/
AD5327.
DECODING MULTIPLE
AD5307/AD5317/AD5327 DEVICES
The SYNC pin on the AD5307/AD5317/AD5327 can be used in
applications to decode a number of DACs. In this application,
all DACs in the system receive the same serial clock and serial
data, but the SYNC to only one of the devices is active at any
given time, allowing access to four channels in this 16-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 44 shows a
diagram of a typical setup for decoding multiple AD5307
devices in a system.
POWER
SCLK
SYNC
DIN
Figure 43. AD5307 in an Opto-Isolated Interface
10kΩ
10kΩ
10kΩ
V
V
V
REGULATOR
DD
DD
DD
5V
SYNC
DIN
SCLK
DCEN
AD5307
V
DD
GND
V
V
REF
REF
V
V
V
V
OUT
OUT
OUT
OUT
10µF
AB
CD
A
B
C
D
0.1µF
Rev. C | Page 21 of 28
ADDRESS
AD5307/AD5317/AD5327 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two of
the DACs in the AD5307/AD5317/AD5327 is shown in Figure 45.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second V
SYNC
SCLK
V
ENABLE
DIN
REF
CODED
5V
SCLK
DIN
Figure 44. Decoding Multiple AD5307 Devices in a System
0.1µF
V
V
SYNC
DIN
SCLK
REF
REF
1G
1A
1B
IN
AB
CD
input is not within the programmed window,
AD5307/
AD5317/
74HC139
AD5327
10µF
GND
DGND
V
V
Figure 45. Window Detection
DD
CC
V
V
V
DD
OUT
OUT
AD5307/AD5317/AD5327
1Y0
1Y1
1Y2
1Y3
A
B
V
IN
CMP04
1/2
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
AD5307
AD5307
AD5307
AD5307
PASS/FAIL
IN
1/6 74HC05
1kΩ
FAIL
signal.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
1kΩ
PASS