AD5326 Analog Devices, AD5326 Datasheet - Page 17

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AD5326

Manufacturer Part Number
AD5326
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5326

Resolution (bits)
12bit
Dac Update Rate
125kSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

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DEFAULT READBACK CONDITIONS
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without first writing to the pointer byte, no
single DAC channel has been specified. In this case, the default
readback bits are all 0 except for the CLR bit and the PD bit,
which are 1.
MULTIPLE DAC WRITE SEQUENCE
Because there are individual bits in the pointer byte for each DAC,
it is possible to write the same data and control bits to two, three,
or four DACs simultaneously by setting the relevant bits to 1.
GAIN
GAIN
GAIN
MSB
MSB
MSB
BUF
BUF
BUF
MOST SIGNIFICANT DATA BYTE
CLR
CLR
CLR
10-BIT AD5316
12-BIT AD5326
8-BIT AD5306
PD
PD
PD
D11
D7
D9
D10
D6
D8
Figure 32. Data Formats for Write and Readback
D7
D5
D9
LSB
LSB
LSB
D6
D8
D4
Rev. F | Page 17 of 24
MSB
MSB
MSB
D3
D5
D7
MULTIPLE DAC READBACK SEQUENCE
If the user attempts to read back data from more than one DAC
at a time, the part reads back the power-on condition of GAIN,
BUF, and data bits (all 0), and the current state of CLR and PD .
D6
D2
D4
LEAST SIGNIFICANT DATA BYTE
D5
D1
D3
10-BIT AD5316
8-BIT AD5306
12-BIT AD5326
D4
D0
D2
D3
D1
0
AD5306/AD5316/AD5326
D0
D2
0
D1
0
0
LSB
LSB
LSB
D0
0
0

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