TDA7439DS13TR STMicroelectronics, TDA7439DS13TR Datasheet - Page 11

• Manufacturer Part Number: TDA7439DS13TR
• Description: IC PROCESSOR BALANCE/TONE 28SOIC
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of TDA7439DS13TR

• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3983-2

TDA7439DS
4
4.1
4.2
4.3
4.4
4.5
I
Data transmission from the microprocessor to the TDA7439DS and vice versa takes place
through the 2-wire I
Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups).
Data validity
The data on the SDA line must be stable during the high period of the clock as shown in
Figure
Start and stop conditions
As shown in
The stop condition is a low to high transition of SDA while SCL is high.
Byte format
Every byte transferred on the SDA line must contain 8 bits. The MSB is transferred first.
There is also provision for an acknowledge bit to follow each byte to indicate that the data
has been received.
Acknowledge
The master (µP) puts a resistive high level on SDA during the acknowledge clock pulse (see
Figure
SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
Transmission without acknowledge
Suppressing the audio processor acknowledge detection enables the µP to use a simpler
transmission: it simply waits for one clock, without checking the slave acknowledging, and
then sends the new data.
This approach has, of course, less protection from transmission errors.
2
C bus interface
12. SDA is allowed to change only when SCL is low.
14). The peripheral (audio processor) that acknowledges has to pull down (low) the
Figure 13
2
C bus interface. This consists of the data and clock lines, SDA and SCL.
a start condition is a high to low transition of SDA while SCL is high.
I
2
C bus interface
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