AD7839 Analog Devices, AD7839 Datasheet
AD7839
Specifications of AD7839
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AD7839 Summary of contents
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... The AD7839 contains eight 13-bit DACs on one monolithic chip. It has output voltages with a full-scale range from reference voltages The AD7839 accepts 13-bit parallel loaded data from the exter nal bus into one of the input registers under the control of the WR, CS and DAC channel address pins, A0– ...
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... NOTES 1 Temperature range for A Version: – + Guaranteed by characterization. Not production tested. 3 The AD7839 is functional with power supplies output amplifier headroom limitations Specifications subject to change without notice 5 + and GND, T ...
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... V 5%; GND = DUTGND = Description Address to WR Setup Time Address to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low Setup Time Hold Time Data Setup Time Data Hold Time Settling Time CLR Pulse Activation Time LDAC Pulsewidth Low t 11 AD7839 ...
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... –4– by more than 0 possible for this to happen IN4148 HP5082-2811 AD7839 DNL Package (LSBs) Option DUTGND_GH OUT 31 V (–)GH REF 30 V (+)GH REF CLR 28 27 ...
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... Level-Triggered Chip Select Input (active low). The device is selected when this input is low. Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7839 input registers. Data is latched into the selected input register on the rising edge of WR. Logic Power Supply ...
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... OUT CLR signal is brought back high, the output voltages from the DACs will reflect the data stored in the relevant DAC registers. Data Loading to the AD7839 Data is loaded into the AD7839 in straight parallel 13-bit wide words. The DAC output voltages, V (+) = +5 V and REF reflect new data in the DAC registers ...
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... TEMPERATURE – C Figure 6. Zero-Scale and Full-Scale Error vs. Temperature 10.19 10.18 10.17 10. SETTLING TIME – s Figure 9. Settling Time (+) –7– AD7839 2 +15V –15V 1 +5V REF(+) V = –5V MAX INL 1.0 REF(–) 0.5 0.0 –0.5 MIN INL –1.0 –1.5 –2.0 –40 – ...
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... V, and V REF 20 V/8192 = 2.44 mV. Analog Output (V ) OUT CONTROLLED POWER-ON OF THE OUTPUT STAGE 2 V (8191/8192 block diagram of the output stage of the AD7839 is shown in REF 2 V (4096/8192) V Figure 13 capable of driving a load parallel with REF 2 V (4095/8192 pF. G REF ...
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... V OUT Figure 16. Output Stage After CLR Is Taken High Power-On with CLR High If CLR is high on the application of power to the device, the output stages of the AD7839 are configured as in Figure 17 while closed and G 1 DAC to the input of its output amplifier. G < ...
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... Digital and ana- log ground planes should be joined at only one place. The GND pin of the AD7839 should be connected to the AGND of the system. If the AD7839 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD7839 ...
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... AD7839. The AD7839 uses nominal reference values achieve DEVICE V OUT an output span Since the AD7839 has a gain of two GND from the reference inputs to the DAC output, adjusting the DEVICE reference voltages by 150 mV will adjust the DAC offset and GND gain by 300 mV ...
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... LOGIC LEVEL SHIFT CONTROLLER DATA BUS Figure 22. Programmable Reference Generation for the AD7839 digital signals driving the DACs need to be level-shifted from the range to the – range. Figure 22 shows a typical application circuit to provide programmable reference capabilities for the AD7839. ...