AD7394 Analog Devices, AD7394 Datasheet - Page 14

• Manufacturer Part Number: AD7394
• Description: +3/+5V Dual, Serial-Input 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7394

• Resolution (bits): 12bit
• Dac Update Rate: 17kSPS
• Dac Settling Time: 60µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser

AD7394
DIGITAL INTERFACE
The AD7394 has a serial data input. A functional block diagram
of the digital section is shown in Figure 22, while Table 2
contains the truth table for the logic control inputs. Three pins
control the serial data input register loading. Two additional
pins determine which DAC receives the data loaded into the
input shift register. Data at the SDI is clocked into the shift
register on the rising edge of the CLK. Data is entered in the
MSB-first format. The active low chip select ( CS ) pin enables
loading of data into the shift register from the SDI pin. Twelve
clock pulses are required to load the 12-bit AD7390 DAC shift
register. If additional bits are clocked into the shift register, for
example, when a microcontroller sends two 8-bit bytes, the
MSBs are ignored (
shift register loading is disabled. The load pins LDA and LDB
control the flow of data from the shift register to the DAC register.
After a new value is clocked into the serial-input register, it is
transferred to the DAC register associated with its LDA or LDB
logic control line. Note, if the user wants to load both DAC
registers with the current contents of the shift register, both
control lines LDA and LDB should be strobed together. The
LDA and LDB pins are level-sensitive and should be returned
to logic high prior to any new data being sent to the input shift
register to avoid changing the DAC register values. See
for a complete set of conditions.
Table 6. Typical Microcontroller Interface Formats
MSB
B15
X
X
1
D11 to D0: 12-bit AD7394 DAC data; X = don’t care; the MSB of byte 1 is the first bit that is loaded into the SDI input.
B14
X
X
Table 6
B13
X
X
). When
BYTE 1
B12
X
X
CS returns to logic high,
D11
X
B11
B10
D10
X
1
Table 2
LSB
B9
D9
D9
Rev. A | Page 14 of 16
B8
D8
D8
CLK
RESET (RS) PIN
Forcing the asynchronous RS pin low sets the DAC register to
all zeros, or midscale, depending on the logic level applied to
the MSB pin. When the MSB pin is set to logic high, both DAC
registers are reset to midscale (that is, the DAC register’s MSB
bit is set to Logic 1 followed by all zeros). The reset function is
useful for setting the DAC outputs to zero at power-up or after
a power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to
a known state. The external reset pulse can be generated by the
microprocessor’s power-on reset signal, by an output from the
microprocessor, or by an external resistor and capacitor. RS has
a Schmitt trigger input, which results in a clean reset function
when using external resistor/capacitor generated pulses. See
Table 2
SDI
CS
MSB
B7
D7
D7
for more information.
B6
D6
D6
EN
REGISTER
SHIFT
Figure 22. Equivalent Digital Interface Logic
D5
B5
D5
Q
L
D
BYTE 0
A
B4
D4
D4
L
D
B
D3
B3
D3
DAC A REGISTER
DAC B REGISTER
D
D
D2
B2
D2
P
P
B1
D1
D1
R
R
R
S
LSB
D0
B0
D0
MSB