AD5320 Analog Devices, AD5320 Datasheet
AD5320
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AD5320 Summary of contents
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... REGISTER INPUT CONTROL LOGIC SYNC SCLK DIN The AD5320 is one of a family of pin-compatible DACs. The AD5300 is the 8-bit version and the AD5310 is the 10-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. PRODUCT HIGHLIGHTS 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. ...
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... Microprocessor Interfacing........................................................... 14 AD5320 to ADSP-2101/ADSP-2103 Interface ....................... 14 AD5320 to 68HC11/68L11 Interface....................................... 14 AD5320 to 80C51/80L51 Interface .......................................... 14 AD5320 to MICROWIRE Interface......................................... 14 Applications..................................................................................... 15 Using REF19x as a Power Supply for AD5320 ....................... 15 Bipolar Operation Using the AD5320 ..................................... 15 Using AD5320 with an Opto-Isolated Interface .................... 15 Power Supply Bypassing and Grounding................................ 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 ...
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... Coming out of power-down mode DAC active and excluding load current and V = GND and V = GND and V = GND and V = GND mA LOAD DD AD5320 ...
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... AD5320 TIMING CHARACTERISTICS 5.5 V, all specifications T DD Table 2. Limit at T Parameter All input signals are specified with (10 See Figure 2. 3 Maximum SCLK frequency is 30 MHz ...
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... Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability. )/θ )/θ Rev Page AD5320 ...
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... The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC Connect AD5320 NC 2 TOP VIEW NC 3 (Not to Scale ...
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... DAC register. Ideally, the output should The zero-code error is always positive in the AD5320 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of zero- code error vs ...
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... AD5320 TYPICAL PERFORMANCE CHARACTERISTICS 25° –4 INL @ 5V –8 –12 –16 0 800 1600 2400 CODE Figure 5. Typical INL Plot 1.0 0.5 0 –0.5 –1.0 0 1000 2000 CODE Figure 6. Typical DNL Plot 25° TUE @ 5V –8 –16 0 800 1600 2400 CODE Figure 7. Typical Total Unadjusted Error Plot ...
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... V DD 1.0 THREE-STATE 0.9 CONDITION 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 3200 4000 0 2.7 Figure 16. Power-Down Current vs. Supply Voltage Rev Page AD5320 TEMPERATURE °C Figure 14. Supply Current vs. Temperature T = 25°C A 3.2 3.7 3.7 4.2 4.7 V (V) DD Figure 15. Supply Current vs. Supply Voltage +105°C +25°C –40°C 3.2 3.7 4 ...
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... AD5320 800 600 400 200 (V) LOGIC Figure 17. Supply Current vs. Logic Input Voltage CLK CH2 V OUT CH1 FULL-SCALE CODE CHANGE 000 HEX – FFF HEX T = 25°C A OUTPUT LOADED WITH 2kΩ AND 200pF TO GND CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 18 ...
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... THEORY OF OPERATION D/A SECTION The AD5320 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no reference input pin, the power supply (V ) acts as the reference. Figure 23 shows a DD block diagram of the DAC architecture. ...
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... AD5320 SERIAL INTERFACE The AD5320 has a 3-wire serial interface ( SYNC , SCLK, and DIN) that is compatible with SPI®, QSPI TM MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK ...
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... POWER-DOWN MODES The AD5320 contains four separate modes of operation. These modes are software-programmable by setting two bits (DB13 and DB12) in the control register. Table 5 shows how the state of the bits corresponds to the mode of operation of the device. Table 5. Modes of Operation for the AD5320 ...
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... P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 output the serial data in a format that has the LSB first. The AD5320 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should consider this. ...
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... The REF19x outputs a steady supply voltage for the AD5320. If the low dropout REF195 is used, the current it needs to supply to the AD5320 is 140 μA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ ...
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... The printed circuit board containing the AD5320 should have separate analog and digital sections, each having its own area of the board. If the AD5320 system where other devices require an AGND to DGND connection, the connec- tion should be made at one point only. This ground point should be as close as possible to the AD5320. The power supply to the AD5320 should be bypassed with 10 μ ...
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... AD5320BRMZ-REEL7 −40°C to +105°C AD5320BRT-500RL7 −40°C to +105°C AD5320BRT-REEL −40°C to +105°C AD5320BRT-REEL7 −40°C to +105°C 1 AD5320BRTZ-500RL7 −40°C to +105°C 1 AD5320BRTZ-REEL −40°C to +105°C 1 AD5320BRTZ-REEL7 −40°C to +105° Pb-free part. 3.20 3 ...
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... AD5320 NOTES Rev Page ...
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... NOTES Rev Page AD5320 ...
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... AD5320 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00934-0-11/05(C) Rev Page ...