ADV7123 Analog Devices, ADV7123 Datasheet - Page 7

• Manufacturer Part Number: ADV7123
• Description: 330 MHz Triple 10-Bit High Speed Video DAC
• Manufacturer: Analog Devices

Specifications of ADV7123

• Resolution (bits): 10bit
• Dac Update Rate: 330MSPS
• Dac Settling Time: 15ns
• Max Pos Supply (v): +5.25V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

Parameter
DAC PERFORMANCE
1
2
3
4
5
5 V TIMING SPECIFICATIONS
V
Table 5.
Parameter
ANALOG OUTPUTS
CLOCK CONTROL
1
2
3
4
5
6
7
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
Timing specifications are measured with input levels of 3.0 V (V
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
Measured from 50% point of full-scale transition to 2% of final value.
Guaranteed by characterization.
f
CLK
AA
Total Harmonic Distortion
Glitch Impulse
DAC-to-DAC Crosstalk
Data Feedthrough
Clock Feedthrough
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
Analog Output Skew
CLOCK Frequency
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay
PSAVE Up Time
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
= 5 V ± 5%,
f
f
f
f
CLK
CLK
CLK
CLK
T
T
= 50 MHz; f
= 50 MHz; f
= 100 MHz; f
= 140 MHz; f
A
MIN
= 25°C
3
to T
MAX
1
6
6
V
MIN
OUT
OUT
REF
7
OUT
OUT
4, 5
4, 5
to T
= 1.00 MHz
= 2.00 MHz
= 1.235 V, R
6
= 2.00 MHz
= 2.00 MHz
3
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
4
5
SET
= 560 Ω, C
L
Symbol
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
CLK
6
7
8
9
1
2
3
4
5
4
5
4
5
PD
10
= 10 pF. All specifications T
IH
) and 0 V (V
Rev. D | Page 7 of 24
IL
Min
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
) 0 for both 5 V and 3.3 V supplies.
Typ
5.5
1.0
15
1
1.0
2
MIN
to T
Max
1.0
2
50
140
240
10
MAX
REF
.
,
2
Min
unless otherwise noted, T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
MHz
MHz
MHz
ns
Typ
66
65
64
64
55
10
23
22
33
Conditions
50 MHz grade
140 MHz grade
240 MHz grade
f
f
f
f
f
f
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
Max
J MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
= 110°C.
ADV7123
Unit
dBc
dBc
dBc
dBc
dBc
pV-sec
dB
dB
dB