AD7302 Analog Devices, AD7302 Datasheet - Page 13

• Manufacturer Part Number: AD7302
• Description: 2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7302

• Resolution (bits): 8bit
• Dac Update Rate: 833kSPS
• Dac Settling Time: 1.2µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

APPLICATIONS
Bipolar Operation Using the AD7302
The AD7302 has been designed for single supply operation,
but bipolar operation is achievable using the circuit shown in
Figure 32. The circuit shown has been configured to achieve an
output voltage range of –5 V < V
at the amplifier output is achievable using an AD820 or OP295
as the output amplifier.
The output voltage for any input code can be calculated as
follows:
where
and
With V
V
Decoding Multiple AD7302 in a System
The CS pin on the AD7302 can be used in applications to
decode a number of DACs. In this application all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to two
channels in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the enable input should
be brought to its inactive state while the coded address inputs are
changing state. Figure 33 shows a diagram of a typical setup for
decoding multiple AD7302 devices in a system. The built-in
power-on reset circuit on the AD7302 ensures that the outputs
of all DACs in the system power up with zero volts on their
outputs.
REV. 0
V
D is the decimal equivalent of the code loaded to the DAC
V
AD589 WITH V
DD
O
REF
EXT REF
AD780/REF192
WITH V
= [(1+R4/R3) (R2/(R1+R2) (2 V
= 5 V.
Figure 32. Bipolar Operation Using the AD7302
is the reference voltage input.
GND
REF
V
OR
IN
DD
V
= 2.5 V, R1 = R3 = 10 k and R2 = R4 = 20 k and
= 5V
DD
OUT
= 3V
0.1µF
V
OUT
= (10
0.1µF
REF IN
AD7302
10µF
AGND
D/256) – 5 V
O
V
DD
< +5 V. Rail-to-rail operation
V
DD
= 5V
REF
DGND
V
OUT
10k
D/256)] – R4 V
R3
A
R1
10k
R2
20k
AD820/
OP295
20k
R4
+5V
–5V
REF
/R3
5V
–13–
AD7302 As a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7302 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B, which
in turn set the limits on the CMP04. If a signal at the V
is not within the programmed window an LED will indicate the
fail condition.
Figure 33. Decoding Multiple AD7302 DACs in a System
DV
+5V
DATA BUS
ADDRESS
DD
ENABLE
CODED
0.1µF
Figure 34. Programmable Window Detector
PD
D7
D0
A/B
CS
WR
CLR
LDAC
10µF
74HC139
AD7302
DGND
1
1A
1B
V
DD
DGND
V
V
DD
CC
V
V
REFIN
AGND
OUT
OUT
1Y0
1Y1
1Y2
1Y3
A
B
V
IN
1/2 CMP04
D0
D8
D0
D8
D0
D8
D0
D8
AD7302
AD7302
AD7302
AD7302
1/6 74HC05
1k
AD7302
PASS/FAIL
FAIL
IN
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1k
input
PASS
A
B
A
B
A
B
A
B