AD9762 Analog Devices, AD9762 Datasheet
AD9762
Specifications of AD9762
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AD9762 Summary of contents
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... It is specified for operation over the industrial tempera- ture range. PRODUCT HIGHLIGHTS 1. The AD9762 is a member of the TxDAC product family which provides an upward or downward component selection path based on resolution ( bits), performance and cost. 2. Manufactured on a CMOS process, the AD9762 uses a pro- ...
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... AD9762–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL +25° MIN MAX Differential Nonlinearity (DNL +25° MIN MAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) ...
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... OUTFS Typ Max 2.5 2 –78 –74 –72 –75 –75 73 AD9762 Units MSPS pA/√Hz pA/√Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9762 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DCOM DB8 DB7 AVDD 5 24 AD9762 DB6 6 23 COMP2 TOP VIEW (Not to Scale) DB5 7 22 IOUTA DB4 8 IOUTB 21 DB3 9 ACOM 20 DB2 10 19 COMP1 DB1 ADJ DB0 12 17 REFIO NC REFLO SLEEP CONNECT PIN DESCRIPTIONS –5– AD9762 ...
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... T . For MIN MAX +5V 0.1 F REFLO COMP1 AVDD ACOM AD9762 50pF PMOS COMP2 CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB FOR DB11–DB3 SWITCHES ...
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... A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9762 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 80 –12dBFS 75 70 0dBFS 0.00 2.00 4.00 6.00 8.00 10.00 FREQUENCY – MHz Figure 5. SFDR vs. f ...
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... AD9762 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 –90 4TH HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 12. THD vs CLOCK MHz OUT 1.25 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 –1.25 0 1000 2000 3000 4000 CODE Figure 15. Typical INL ...
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... A – dBFS OUT Figure 28. Single-Tone SFDR vs OUT OUT CLOCK –9– AD9762 = +25 C, SFDR up to Nyquist, unless otherwise noted –12dBFS 75 70 –6dBFS 65 0dBFS FREQUENCY – MHz Figure 23 ...
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... AD9762 –70 –75 2ND HARMONIC 3RD –80 HARMONIC –85 4TH –90 HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 30. THD vs CLOCK OUT 2 MHz 1.25 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 –1.25 0 1000 2000 3000 4000 CODE Figure 33. Typical INL 100 MSPS ...
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... FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9762. The AD9762 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the 5 most significant bits (MSBs). The next 4 bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... SET AD9762 Figure 41. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9762 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a V-I converter as shown in Figure 41, such that its current output, I the ratio of the V ...
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... Since the output currents of I complementary, they become additive when processed differen- tially. A properly selected transformer will allow the AD9762 to provide the required power and voltage levels to different loads. Refer to Applying the AD9762 section for examples of various output configurations. The output impedance of I AVDD equivalent parallel combination of the PMOS switches associ- ated with the current sources and is typically 100 kΩ ...
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... AD9762 remains enabled if this input is left disconnected. DIGITAL INPUT Figure 46. Equivalent Digital Input Since the AD9762 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum set-up and hold times of the AD9762 as well as its required min/max input logic level thresholds ...
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... DVDD REV. B APPLYING THE AD9762 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9762. Unless otherwise noted assumed that I OUTFS ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration ...
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... In this case, AVDD which is the positive analog supply for both the AD9762 and the op amp is also used to level-shift the differ- ential output of the AD9762 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... Figure 55. Differential LC Filter for Single + Applications Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9762. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- port, etc. In mixed signal design, the analog and digital portions ...
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... AD9762 in any application where high R R LOAD LOAD resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9762 in various configurations. Possible output configurations include TO transformer coupled, resistor terminated, inverting/noninverting NYQUIST FILTER and differential amplifier outputs. The digital inputs are designed ...
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... REV. B Figure 59. AD9762 Evaluation Board Schematic –19– AD9762 ...
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... AD9762 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) –20– REV. B ...
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... REV. B Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) –21– AD9762 ...
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... AD9762 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom –22– REV. B ...
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... SEATING 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0091 (0.23) BSC 28-Lead, TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 0.0433 (1.10) MAX 8 0 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –23– AD9762 0.0291 (0.74) 45 0.0098 (0.25 0.0500 (1.27) 0.0157 (0.40) 0.028 (0.70) 0.020 (0.50) ...