DAC8562 Analog Devices, DAC8562 Datasheet - Page 15

• Manufacturer Part Number: DAC8562
• Description: +5 Volt, Parallel Input Complete 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of DAC8562

• Resolution (bits): 12bit
• Dac Update Rate: 62.5kSPS
• Dac Settling Time: 16µs
• Max Pos Supply (v): +5.25V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

REV. A
DAC8562 – M68HC11 Interface Program Source Code
*
* DAC8562 to M68HC11 Interface Assembly Program
* Adolfo A. Garcia
* September 14, 1992
*
* M68HC11 Register definitions
*
PORTB
PORTC
*
DDRC
*
* RAM variables:
*
*
*
MSBS
LSBS
*
* Main Program
*
INIT
*
* Initialize Port C Outputs
*
*
*
* Call update subroutine
*
*
* Subroutine UPDATE
*
UPDATE PSHX
*
* Enter contents of the Hi-byte input register
*
*
* Enter Contents of’ Lo-byte input register
*
*
*
* Clear DAC output to zero
*
*
* Loading input buffer latches
*
TFRLP
*
EQU
EQU
EQU
EQU
EQU
ORG
LDS
LDAA
STAA
LDAA
STAA
BSR
JMP
PSHY
PSHA
LDAA
STAA
LDAA
STAA
LDX
LDY
BCLR
BSET
BSET
LDAA
STAA
INX
CPX
BEQ
BCLR
BRA
$1004
$1003
$1007
$00
$01
$C000
#$CFFF
#$07
DDRC
#$06
PORTC
UPDATE
$E000
#$0A
MSBS
#$AA
LSBS
#MSBS
#$1000
PORTC,Y $04
PORTC,Y $04
PORTC,Y $01
0,X
PORTB
#LSBS+1
DUMP
PORTC,Y $01
TFRLP
Port C control register
“0,0,0,0;0,CLR/,CE/,MSB-LSB/”
Port C data direction
MSBS are encoded from 0 (Hex) to F (Hex)
LSBS are encoded from 00 (Hex) to F (Hex)
DAC requires two 8-bit loads
Hi-byte: “0,0,0,0;MSB,DB10,DB9,DB8”
Lo-byte: “DB7,DB6,DB5,DB4;DB3,DB2,
DB1,DB0”
Start of user’s RAM in EVB
Top of C page RAM
0,0,0,0;0,1,1,1
CLR/,CE/, and MSB-LSB/ are now enabled
as outputs
0,0.0,0;0,1,1,0
CLR/-Hi, CE/-Hi, MSB-LSB/-Lo
Initialize Port C Outputs
Xfer 2 8-bit words to DAC8562
Restart BUFFALO
Save registers X, Y, and A
0,0,0,0;1,0,1,0
MSBS are set to 0A (Hex)
1,0,1,0;1,0,1,0
LSBS are set to AA (Hex)
Stack pointer at 1st byte to send via Port B
Stack pointer at on-chip registers
Assert CLR/
De-assert CLR/
Set hi-byte register load
Get a byte to transfer via Port B
Write data to input register
Increment counter to next byte for transfer
Are we done yet ?
If yes, update DAC output
Latch hi-byte register and set lo-byte register
load
–15–
DAC8562–M68HC11 Interface Program Source Code (Continued)
* Update DAC output with contents of input registers
*
DUMP
*
BCLR
BSET
PULA
PULY
PULX
RTS
PORTC,Y $02
PORTC,Y $02
Assert CE/
Latch DAC register
When done, restore registers X, Y & A
** Return to Main Program **
DAC8562