AD7837 Analog Devices, AD7837 Datasheet - Page 8

• Manufacturer Part Number: AD7837
• Description: LC2MOS Complete, Dual 12-Bit MDAC, (8 + 4) Loading Structure
• Manufacturer: Analog Devices

Specifications of AD7837

• Resolution (bits): 12bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte

AD7837/AD7847
CS, WR, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided that
LDAC is held high, there is no analog output change as a result
of loading data to the input latches. Address lines A0 and A1
determine which latch data is loaded to when CS and WR are low.
The control logic truth table for the part is shown in Table II.
CS WR A1 A0 LDAC Function
1
X
0
0
0
0
1
X = Don’t Care.
The LDAC input controls the transfer of 12-bit data from the
input latches to the DAC latches. When LDAC is taken low, both
DAC latches, and hence both analog outputs, are updated at
the same time. The data in the DAC latches is held on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in the
simultaneous updating of multiple AD7837s. However, care must
be taken while exercising LDAC during a write cycle. If an LDAC
operation overlaps a CS and WR operation, there is a possibility
of invalid data being latched to the output. To avoid this, LDAC
must remain low after CS or WR return high for a period equal
to or greater than t
A0/A1
LDAC
DATA
WR
CS
X
1
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
Table II. AD7837 Truth Table
8
1
1
1
1
1
1
0
, the minimum LDAC pulsewidth.
t
t
6
1
ADDRESS DATA
t
t
VALID
DATA
3
4
No Data Transfer
No Data Transfer
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
t
t
2
5
t
7
t
8
UNIPOLAR BINARY OPERATION
Figure 15 shows DAC A on the AD7837/AD7847 connected
for unipolar binary operation. Similar connections apply for
DAC B. When V
rant multiplication. The code table for this circuit is shown in
Table III. Note that on the AD7847 the feedback resistor R
internally connected to V
DAC Latch Contents
MSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Note 1 LSB =
V
IN
LSB
V
4096
V
REFA
AD7837
AD7847
IN
Table III. Unipolar Code Table
IN
DGND
.
DAC A
is an ac signal, the circuit performs 2-quad-
AGNDA
OUT
V
V
DD
DD
.
Analog Output, V
0 V
–V
–V
–V
IN
IN
IN
×
×
×
V
V
SS
SS









V
R
OUTA
4096
2048
4096
4096
4095
FBA
1
CONNECTED
ON AD7847




 = –1/ 2 V




INTERNALLY
OUT
V
OUT
FB
IN
is