AD8551 Analog Devices, AD8551 Datasheet - Page 16

• Manufacturer Part Number: AD8551
• Description: Zero-Drift, Single-Supply, RRIO Single Op Amp
• Manufacturer: Analog Devices

Specifications of AD8551

• -3db Bandwidth: 1.5MHz
• Slew Rate: 0.4V/µs
• Vos: 1µV
• Ib: 10pA
• # Opamps Per Pkg: 1
• Input Noise (nv/rthz): 42nV/rtHz
• Vcc-vee: 2.7V to 6V
• Isy Per Amplifier: 975µA
• Packages: SOIC,SOP

AD8551/AD8552/AD8554
earn the reputation of being among the most precise amplifiers
available on the market.
HIGH GAIN, CMRR, PSRR
Common-mode and power supply rejection are indications
of the amount of offset voltage an amplifier has as a result of a
change in its input common-mode or power supply voltages. As
shown in the previous section, the autocorrection architecture
of the AD855x allows it to quite effectively minimize offset volt-
ages. The technique also corrects for offset errors caused by
common-mode voltage swings and power supply variations.
This results in superb CMRR and PSRR figures in excess of
130 dB. Because the autocorrection occurs continuously, these
figures can be maintained across the entire temperature range
of the device, from −40°C to +125°C.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD855x, care is
needed in laying out the circuit board. The PC board surface
must remain clean and free of moisture to avoid leakage cur-
rents between adjacent traces. Surface coating of the circuit
board reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board. The use of guard
rings around the amplifier inputs further reduces leakage cur-
rents. Figure 52 shows proper guard ring configuration, and
Figure 53 shows the top view of a surface-mount layout. The
guard ring does not need to be a specific width, but it should
form a continuous loop around both inputs. By setting the
guard ring voltage equal to the voltage at the noninverting
input, parasitic capacitance is minimized as well. For further
reduction of leakage currents, components can be mounted to
the PC board using Teflon standoff insulators.
V
GUARD
V
IN
IN1
RING
Figure 53. Top View of AD8552 SOIC Layout with Guard Rings
V
Figure 52. Guard Ring Layout and Connections to Reduce
REF
R
1
V
IN
AD8552
R
2
PC Board Leakage Currents
V–
AD8552
V
OUT
AD8552
V
IN
V+
V
R
OUT
2
AD8552
R
V
1
REF
GUARD
RING
V
V
IN2
OUT
Rev. D | Page 16 of 24
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most
common metallic junctions on a circuit board are solder-to-
board trace and solder-to-component lead. Figure 54 shows a
cross-section of the thermal voltage error sources. If the
temperature of the PC board at one end of the component (T
is different from the temperature at the other end (T
resulting Seebeck voltages are not equal, resulting in a thermal
voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on
the circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and reduces
EMI noise pickup.
V
COPPER
TS1
TRACE
V
COMPONENT
SC1
+
LEAD
+
NOTES
1. R
T
ALIGNMENT TO R
A1
S
Figure 54. Mismatch in Seebeck Voltages Causes
V
Figure 55. Using Dummy Components to Cancel
SHOULD BE PLACED IN CLOSE PROXIMITY AND
IN
Thermoelectric Voltage Errors
Thermoelectric Voltage Error
R
S
SURFACE-MOUNT
R
= R
1
COMPONENT
1
PC BOARD
1
TO BALANCE SEEBECK VOLTAGES.
R
A
F
V
IF T
V
AD8551/
AD8552/
AD8554
= 1 + (R
TS1
A1
+ V
≠ T
F
SC1
T
/R
A2
A2
1
, THEN
≠ V
)
V
+
OUT
TS2
V
SC2
+
+ V
A2
V
), the
TS2
SC2
SOLDER
A1
)