AD823 Analog Devices, AD823 Datasheet - Page 13

• Manufacturer Part Number: AD823
• Description: Dual, 16 MHz, Rail-to-Rail FET Input Amplifier
• Manufacturer: Analog Devices

Specifications of AD823

• -3db Bandwidth: 16MHz
• Slew Rate: 25V/µs
• Vos: 700µV
• Ib: 5pA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 16nV/rtHz
• Vcc-vee: 3V to 36V
• Isy Per Amplifier: 4.2mA
• Packages: DIP,SOIC

Data Sheet
THEORY OF OPERATION
The AD823 is fabricated on the Analog Devices, Inc. proprietary
complementary bipolar (CB) process that enables the construction
of PNP and NPN transistors with similar f
800 MHz region. In addition, the process also features N-Channel
JFETs that are used in the input stage of the AD823. These
process features allow the construction of high frequency, low
distortion op amps with picoamp input currents. This design
uses a differential output input stage to maximize bandwidth
and headroom (see Figure 36). The smaller signal swings
required on the S1P/S1N outputs reduce the effect of the
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic
distortion of better than −91 dB @ 20 kHz into 600 Ω with
V
complementary common emitter design of the output stage
provides excellent load drive without the need for emitter
followers, thereby improving the output range of the device
considerably with respect to conventional op amps. The
AD823 can drive 20 mA with the outputs within 0.6 V of the
supply rails. The AD823 also offers outstanding precision for a
high speed op amp. Input offset voltages of 1 mV maximum
and offset drift of 2 µV/°C are achieved through the use of the
Analog Devices advanced thin film trimming techniques.
OUT
= 4 V p-p on a single 5 V supply is achieved. The
V
V
V
V
INN
INP
CC
EE
J1
R42
I1
R37
J6
C6
Q72
Q53
T
’s in the 600 MHz to
R33
S1P
Q48
V
V
BE
CC
I2
+ 0.3V
Q35
Q61
Figure 36. Simplified Schematic
R43
S1N
V1
Rev. E | Page 13 of 20
Q46
I5
I3
Q21
A nested integrator topology is used in the AD823 (see Figure 37).
The output stage can be modeled as an ideal op amp with a
single-pole response and a unity-gain frequency set by
transconductance g
impedance of the input stage; g
C1 and C5 provide Miller compensation for the overall op amp.
The unity-gain frequency occurs at g
equations for this circuit yields
where:
A0 = g
A2 = g
The first pole in the denominator is the dominant pole of the
amplifier and occurs at ~18 Hz. This equals the input stage
output impedance R1 multiplied by the Miller-multiplied value
of C1. The second pole occurs at the unity-gain bandwidth of
the output stage, which is 23 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard 2-stage architecture would allow.
Q56
Q43
Q62
Q58
R44
V
Vi
m
m2
OUT
g
m2
R2 (open-loop gain of output stage).
R28
V
=
B
R2R1 (open-loop gain of op amp).
Q49
Q60
Q52
Q55
(
sR1
[
Q54
C1
m2
I6
(
I4
A2
Q18
and Capacitor C2. R1 is the output
+
Q59
A = 1
Q44
A = 1
1
)
]
A0
+
C2
C1
1
m
)
×
is the input transconductance.




Q57
A = 19
Q17
A = 19
s



m
g
/C5. Solving the node
C2
m
V
2
OUT



+
1




AD823