ADM8691 Analog Devices, ADM8691 Datasheet - Page 7

• Manufacturer Part Number: ADM8691
• Manufacturer: Analog Devices

Specifications of ADM8691

• Product Description: µP Supv w/ Backup Batt Switch, Adj Reset Period, Adj Watchdog Period, 4.65V Trip point, 100 mA Iout
• Supply Current: 200µA
• Us Price 1000-4999: n/a
• Display In Ist: Yes
• Active For Param Search: Yes

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
8-Lead
8
1
2
3
N/A
N/A
N/A
N/A
4
5
6
N/A
N/A
N/A
Pin No.
2
3
4
5
10
16-Lead
1
6
7
8
9
11
12
13
14
Figure 3.
V
GND
V
OUT
PFI
8-Lead PDIP and 8-Lead SOIC_N
CC
1
2
3
4
ADM8690
(Not to Scale)
ADM8690
V
V
V
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
PFO
WDI
CE
CE
WDO
Mnemonic
TOP VIEW
BATT
OUT
CC
OUT
IN
Pin Configuration,
8
7
6
5 PFO
V
RESET
WDI
BATT
Description
Backup Battery Input. V
highest potential.
Output Voltage. V
potential. V
are not used.
Power Supply Input. 5 V nominal. V
at the highest potential.
Ground. This is the 0 V ground reference for all signals.
Logic Output. BATT ON goes high when V
when V
base of an external PNP transistor to increase the output current above the 100 mA rating of V
Logic Output. LOW LINE goes low when V
soon as V
Oscillator Logic Input. When OSC SEL is low, OSC IN can be driven by an external clock signal, or
an external capacitor can be connected between OSC IN and GND. This sets both the reset active
pulse timing and the watchdog timeout period (see Table 5 and Figure 17 through Figure 20).
When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is
fixed at 50 ms typical (ADM8691) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects either the fast (100 ms) or slow (1.6 sec) watchdog timeout period. In both modes, the
timeout period immediately after a reset is 1.6 sec typical.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal
oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled (see Table 5). OSC SEL has a 5 μA internal pull-up.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than
1.3 V, PFO goes low. Connect PFI to GND or V
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less
than 1.3 V. The comparator is turned off and PFO goes low when V
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than
the watchdog timeout period, RESET pulses low and WDO goes low. The timer is reset with each
transition on the WDI line. The watchdog timer can be disabled if WDI is left floating or is driven
to midsupply.
Logic Output. CE
threshold. If V
Logic Input. Input to the CE gating circuit. When not in use, connect this pin to GND or V
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer
than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is
unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also
goes high when LOW LINE goes low.
OUT
CC
is internally switched to V
OUT
rises above the reset threshold.
CC
can supply up to 100 mA to power CMOS RAM. Connect V
is below the reset threshold, CE
OUT
CC
Rev. C | Page 7 of 24
is a gated version of the CE
or V
BATT
BATT
or V
is internally switched to V
CC
is internally switched to V
CC
CC
. The output typically sinks 35 mA and can directly drive the
or V
Figure 4.
BATT
16-Lead SOIC_N, 16-Lead SOIC_W, and 16-Lead TSSOP
OUT
CC
falls below the reset threshold. It returns high as
OUT
is internally switched to V
is internally switched to the V
ADM8691/ADM8695
IN
signal. CE
OUT
LOW LINE
when not used.
BATT ON
OSC SEL
ADM8690/ADM8691/ADM8695
OSC IN
is forced high. See
V
V
BATT
GND
V
OUT
OUT
CC
, depending on which is at the highest
OUT
1
2
3
4
5
6
7
8
OUT
ADM8691/
(Not to Scale)
ADM8695
tracks CE
TOP VIEW
, depending on which is at the
Pin Configuration, 16-Lead PDIP,
CC
is below V
IN
Figure 21
OUT
when V
16
15
14
13
12
11
10
9
OUT
, depending on which is
RESET
RESET
WDO
CE
CE
WDI
PFO
PFI
BATT
to V
IN
OUT
CC
input. It goes low
BATT
and
CC
is above the reset
.
if V
Figure 22
OUT
and V
OUT
.
.
BATT
OUT
.