ADP1655 Analog Devices, ADP1655 Datasheet - Page 6

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ADP1655

Manufacturer Part Number
ADP1655
Description
Dual LED Flash Driver with I2C Compatible Interface
Manufacturer
Analog Devices
Datasheet

Specifications of ADP1655

Product Description
Serial 2 WLED Flash Driver
Led #
2
Led Configuration
Serial
Topology
Inductive
Application
Flash
I2c Support
Yes
Max Iout (ma)
400mA
Brightness Control
I2C
Peak Efficiency (%)
n/a
Switching Frequency
2MHz
Over Volt Protection (v)
10V
Vin Min (v)
2.5V
Vout (v)
Current Output
Synchronous
Yes
Package
12-Bump WLCSP
ADP1655
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN, SDA/EN2, SCL/EN1, I2C/EN,
STROBE, TORCH, TX_MASK to SGND
LED_OUT, SW, VOUT to SGND
PGND to SGND
VOUT to LED_OUT
Ambient Temperature Range (T
Junction Temperature Range (T
Storage Temperature
ESD Human Body Model
ESD Charged Device Model
ESD Machine Model
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
The ADP1655 may be damaged if the junction temperature
limits are exceeded. Monitoring T
is within the specified temperature limits. In applications with
high power dissipation and poor thermal resistance, the maximum
T
dissipation and low PCB thermal resistance, the maximum T
can exceed the maximum limit as long as the T
fication limits. T
dissipation (PD) of the device, and the junction-to-ambient
thermal resistance (θ
calculated from the T
A
may have to be derated. In applications with moderate power
T
J
= T
A
+ (PD × θ
J
of the device is dependent on the T
JA
A
JA
) of the package. Maximum T
and PD using the following formula:
)
A
J
)
)
A
does not guarantee that T
Rating
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
±2000 V
±1000 V
±200 V
J
is within speci-
A
, the power
J
is
A
Rev. 0 | Page 6 of 24
J
THERMAL RESISTANCE
θ
a 4-layer board. θ
board layout. In applications where high maximum power dissi-
pation exists, attention to thermal board design is required. The
value of θ
environmental conditions. The specified value of θ
on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, per JEDEC
standards. For more information, see the AN-617 Application
Note, MicroCSP
θ
Table 3. Thermal Resistance
Package Type
12-Ball WLCSP
ESD CAUTION
JA
JA
of the package is based on modeling and calculation using
is specified for a device mounted on a JEDEC 2S2P PCB.
JA
may vary, depending on PCB material, layout, and
TM
JA
Wafer Level Chip Scale Package.
is highly dependent on the application and
θ
75
JA
JA
Unit
°C/W
is based

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