ADM6820 Analog Devices, ADM6820 Datasheet
ADM6820
Specifications of ADM6820
Available stocks
Related parts for ADM6820
ADM6820 Summary of contents
Page 1
... GATE is driven high and the secondary supply is enabled. The ADM6820 has only one comparator that is on the SETV pin. It also features a timeout period that is adjustable via a single external capacitor on the SETD pin. ...
Page 2
... ADM6819/ADM6820 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagrams.............................................................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 REVISION HISTORY 7/06—Rev. 0: Initial Version Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 10 SETV Pin ..................................................................................... 10 EN Pin.......................................................................................... 10 GATE Pin ...
Page 3
... ADM6819 3 ADM6820 V falling CC V rising, enables GATE SETV V falling, disables GATE SETV V > > V (ADM6819) SETV ADM6820 T = 25° 1500 pF 3 7.8 V GATE CC2 GATE C = 1500 pF 3 0.5 V GATE CC2 GATE With respect > 50 MΩ CCx ...
Page 4
... ADM6819/ADM6820 TIMING DIAGRAMS V CC1 V CC2 R3 R4 Figure 2. ADM6819 Solution for Validating Two Supplies Before Sequencing V SETV V GATE Figure 3. ADM6819/ADM6820 Timing Diagram Using SETV for Sequencing V SETV GATE V V CC1 CC2 CHARGE PUMP UVLO R1 LOGIC SETV DRIVER 0.618V R2 0.618V ADM6819 GND EN 0 ...
Page 5
... 3. 3. CC2 GATE V CC1 ADM6819/ R1 ADM6820 EN/SETD SETV GND R2 Figure 5. ADM6819/ADM6820 Solution for Sequencing Three Supply Rails Q1 V CC2 GATE V CC1 ADM6819/ R3 ADM6820 EN/SETD SETV GND R4 Rev Page ADM6819/ADM6820 OUT V = 3.3V OUT 3.0V OUT ...
Page 6
... ADM6819/ADM6820 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter CC1 CC2 SETV, SETD, EN GATE Storage Temperature Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
Page 7
... CC2 ADM6820 GND TOP VIEW GATE 2 5 (Not to Scale) SETV SETD 3 4 Figure 7. ADM6820 Pin Configuration or V must be greater than the UVLO to enable external CC2 after EN is driven high. GATE drive is DELAY 6 (s) = 2.652 × 10 × C (F). DELAY SET and ENABLE is driven high. GATE drive ENABLE is driven low ...
Page 8
... ADM6819/ADM6820 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0. 3.3V, V CC2 CC1 0.40 0. 5V, V CC1 CC1 CC2 0.30 0.25 0.20 0.15 0.10 –50 – TEMPERATURE (°C) Figure 8. Supply Current vs. Temperature 0. CC1 0. SETV 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0. (V) CC2 Figure 9. I vs. V CC2 CC2 0. 3.3V CC1 0. SETV ...
Page 9
... TEMPERATURE (°C) Figure 15. t vs. Temperature DELAY V SETV V GATE 5V/DIV V = 3.3V CC1 SETV GATE 5V/DIV 125 150 Rev Page ADM6819/ADM6820 C = 1500pF LOAD 20µs/DIV Figure 16. Gate Turn-Off Time C = 1500pF LOAD 1ms/DIV Figure 17. Gate Turn-On Time ...
Page 10
... OUT FET switches on after the delay timer expires. On the ADM6820, this delay is programmable using a capacitor on the SETD pin. On the ADM6819, this delay is fixed at 300 ms and the EN pin must be valid high to begin the timer. The required turn-on voltage is calculated by the following equation: ...
Page 11
... SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 20. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Package Description 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23] Rev Page ADM6819/ADM6820 10° 0.60 4° 0.45 0° 0.30 Package Option RJ-6 RJ-6 Branding M2R ...
Page 12
... ADM6819/ADM6820 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05113-0-7/06(0) Rev Page ...