ADM1062 Analog Devices, ADM1062 Datasheet - Page 7

• Manufacturer Part Number: ADM1062
• Manufacturer: Analog Devices

Specifications of ADM1062

• # Supplies Monitored: 10
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 10
• Fet Drive/enable Output: Both
• Voltage Readback: 12-bit ADC
• Supply Adj/margining: 12-bit ADC+6 DACs
• Package: 40 ld LFCSP ,48 ld TQFP

Parameter
DIGITAL INPUTS (VXx, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
SERIAL BUS TIMING
SEQUENCING ENGINE TIMING
1
2
3
4
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
Specification is not production tested but is supported by characterization data at initial product release.
Timing specifications are guaranteed by design and supported by characterization data.
Three-State Output Leakage Current
Oscillator Frequency
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Programmable Pull-Down Current, I
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
State Change Time
I
I
R
I
OL
SINK
SOURCE
PULL-UP
3
3
(VPx)
3
BUF
LOW
HIGH
4
HD;STA
HD;DAT
SCLK
SU;STA
SU;STO
SU;DAT
IL
IL
F
IL
IH
IL
R
IH
IH
OL
3
PULL-DOWN
Min
16
90
2.0
−1
2.0
1.3
0.6
0.6
0.6
1.3
0.6
100
5
Typ
20
100
5
20
10
Rev. C | Page 7 of 36
Max
20
60
29
2
10
110
0.8
1
0.8
0.4
400
300
300
1
Unit
mA
mA
kΩ
mA
μA
kHz
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μA
μs
Test Conditions/Comments
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
V
All on-chip time delays derived from this clock
Maximum V
Maximum V
V
V
VDDCAP = 4.75 V T
I
V
OUT
PDO
IN
IN
IN
= 5.5 V
= 0 V
= 0 V
= −3.0 mA
= 14.4 V
IN
IN
= 5.5 V
= 5.5 V
A
= 25°C if known logic state is required
ADM1062