ADUC812 Analog Devices, ADUC812 Datasheet
ADUC812
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ADUC812 Summary of contents
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... DAS and Communications Systems Control Loop Monitors (Optical Networks/Base Stations) GENERAL DESCRIPTION The ADuC812 is a fully integrated 12-bit data acquisition system incorporating a high performance self-calibrating multichannel ADC, dual DAC, and programmable 8-bit MCU (8051 instruc- tion set compatible single chip. ...
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... ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . . . . 20 Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Using the Flash/EE Memory Interface . . . . . . . . . . . . . . . . . . 20 Erase-All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Using the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . 24 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . 25 MISO (Master In, Slave Out Data I/O Pin MOSI (Master Out, Slave In Pin SCLOCK (Serial Clock I/O Pin) ...
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... V µA max µA typ pF max mV typ Can vary significantly (> ±20%) mV/°C typ from device to device Bits LSB typ LSB typ Guaranteed 12-Bit Monotonic mV max mV typ mV max mV typ % typ % of Full-Scale on DAC1 V typ V typ kΩ typ pF typ Ω typ µA typ ADuC812 ...
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... XTAL1 Input High Voltage (V ) Only INH Input Low Voltage (V ) INL Input Leakage Current (Port 0, EA) Logic 1 Input Current (All Digital Inputs) Logic 0 Input Current (Port Logic 1-0 Transition Current (Port –700 Input Capacitance ADuC812BS Unit µs typ 10 ...
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... User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent. 7 The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate. 8 SNR calculation includes distortion and noise components. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Storage Temperature Range . . . . . . . . . . . . – ...
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... REV. E PIN FUNCTION DESCRIPTIONS 2 C Compatible or SPI Data Input/Output Pin Compatible or SPI Serial Interface Clock. –7– ADuC812 ...
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... ADuC812 Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET ...
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... The SFR space is mapped in the upper 128 bytes of internal data SPACE memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC812 via the SFR area is shown in Figure 3. FFFFFFH 8K BYTE ELECTRICALLY REPROGRAMMABLE ...
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... ADuC812 OVERVIEW OF MCU-RELATED SFRs Accumulator SFR ACC is the Accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator SFR The B register is used with the ACC for multiplication and division operations ...
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... FFH 81H 07H THESE BITS ARE CONTAINED IN THIS BYTE. MNEMONIC TCON IT0 IE0 89H 0 88H 0 DEFAULT VALUE 88H 00H SFR ADDRESS –11– ADuC812 “1” DAC0H DAC1L DAC1H DACCON RESERVED FDH 04H FAH 00H FBH 00H FCH 00H ADCOFSH ...
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... RAM space without any interaction from the MCU core. This automatic capture facility can extend through a 16 MByte external Data Memory space. The ADuC812 is shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power-up, ensuring optimum ADC performance. The ADC core contains internal offset and gain calibration registers ...
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... Table III. ADCCON1 SFR Bit Designations ADC powered down ADC normal mode ADC powered down if not executing a conversion cycle ADC standby if not executing a conversion cycle circuits are maintained on, whereas all ADC peripherals are REF –13– ADuC812 ...
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... ADuC812 ADCCON2—(ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default Value 00H ocation Name Description L ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion ...
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... Absolute Maxi- mum Ratings. They are not necessary if the op amp is powered from the same supply as the ADuC812 since in that case, the op amp is unable to generate voltages above amp is necessary unless the signal source is very low imped- ADuC812 ance to begin with. DC leakage currents at the ADuC812’ ...
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... ADC DMA Mode The on-chip ADC has been designed to run at a maximum conversion speed of 5 µs (200 kHz sampling rate). When con- verting at this rate, the ADuC812 MicroConverter has 5 µs to read the ADC result and store the result in memory for further to circumvent DD postprocessing, otherwise the next ADC sample could be lost ...
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... ADuC812 core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz). DMA Mode Configuration Example To set the ADuC812 into DMA mode, a number of steps must be followed. 1. The ADC must be powered down by setting MD1 and MD0 ADCCON1. ...
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... REF which equates to ±2.5% of the reference voltage. Calibration Each ADuC812 is calibrated in the factory prior to shipping, and the offset and gain calibration coefficients are stored in a hidden area of FLASH/EE memory. Each time the ADuC812 powers up, an internal power-on configuration routine copies these coefficients into the offset and gain calibration registers in the SFR area ...
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... Using the Flash/EE Program Memory This 8K byte Flash/EE program memory array is mapped into the lower 8K bytes of the 64K bytes program space address- able by the ADuC812 and will be used to hold user code in typical applications. The program memory array can be programmed in one of two modes: ...
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... Table VII. It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC812 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory ...
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... The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC812 incorporates two 12-bit voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable DAC Control DACCON ...
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... Figure 19. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 19 get worse as a function of output loading. Most of the ADuC812’s data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 19 become larger ...
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... DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24, respectively Figure 23. DAC Output Spike at Chip Power-Up 5 ADuC812 Figure 24. DAC Output Spike at DAC Enable –23– ADuC812 200 s/DIV AV – 2V/DIV DD DAC OUT – 500mV/DIV s/DIV, 1V/DIV ...
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... ADuC812 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error. The Watch- dog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When ...
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... DD supply caused the fault condition. DD SERIAL PERIPHERAL INTERFACE The ADuC812 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins are shared with the I therefore the user can only enable one or the other interface at any given time (see SPE in Table XI) ...
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... To configure this pin as a digital input, the bit must be cleared, e.g., CLR P1.5. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC812 to be used in single master, multislave SPI configurations. If CPHA = 1, then the SS input may be permanently pulled low. ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC812 needs to assert the SS pin on an external slave device, a Port digital output pin should be used. ...
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... ADuC812 COMPATIBLE INTERFACE The ADuC812 supports a 2-wire serial interface mode that compatible. The I C compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in Table IX). ...
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... These remaining functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O Ports 0–3 The ADuC812 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral features on the device ...
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... ADuC812 User configuration and control of all Timer operating modes is achieved via three SFRs: TMOD, TCON Control and configuration for Timers 0 and 1. T2CON Control and configuration for Timer 2. Timer/Counter 0 and TMOD 1 Mode Register SFR Address 89H Power-On Default Value 00H Bit Addressable ...
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... Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. REV Table XVI. TCON SFR Bit Designations –31– ADuC812 ...
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... ADuC812 TIMER/COUNTERS 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler ...
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... SFR Address = CDH, CCH, respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload high byte and low byte. SFR Address = CBH, CAH, respectively. REV Table XVII. T2CON SFR Bit Designations –33– ADuC812 ...
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... ADuC812 Timer/Counter Operation Modes The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XVIII. Table XVIII. TIMECON SFR Bit Designations RCLK (or) TCLK CAP2 TR2 16-Bit Autoreload Mode In Autoreload mode, there are two options, which are selected by bit EXEN2 in T2CON ...
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... Table XIX. SCON SFR Bit Designations SM1 Selected Operating Mode 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 1 Mode 1: 8-bit UART, variable baud rate 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 Mode 3: 9-bit UART, variable baud rate –35– ADuC812 ...
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... ADuC812 Mode 0 (8-Bit Shift Register Mode) Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. ...
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... CONTROL TIMER 2 OVERFLOW TL2 TH2 (8 BITS) (8 BITS) TR2 RELOAD RCAP2L RCAP2H EXF TIMER 2 2 INTERRUPT CONTROL EXEN2 Figure 34. Timer 2, UART Baud Rates –37– ADuC812 = Modes and Baud Rate × Timer Overflow Rate × − ...
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... ADuC812 INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register IE2 Secondary Interrupt Enable Register Interrupt Enable ...
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... The interrupt vector addresses are shown in the Table XXVI. Table XXVI. Interrupt Vector Addresses Source IE0 TF0 IE1 TF1 TF2 + EXF2 ADCI I2CI + ISPI PSMI –39– ADuC812 — Vector Address 0003H 000BH 0013H ...
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... Note that a second very important function of the EA pin is described in the Single Pin Emulation Mode section. External program memory (if used) must be connected to the ADuC812 as illustrated in Figure 37. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus ...
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... Timing Specifica- tion sections. Power-On Reset Operation External POR (power-on reset) circuitry must be implemented to drive the RESET pin of the ADuC812. The circuit must hold the RESET pin asserted (high) whenever the power supply ( below 2.5 V. Furthermore ...
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... Of course, the user must add any currents sourced by the DAC or the parallel and serial I/O pins, in order to determine the total current needed at the ADuC812’s supply pins. Also, current drawn from the DV increase by approximately 10 mA during Flash/EE erase and program cycles ...
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... If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC812’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC812 input pins ...
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... ADuC812. In addition to the basic UART connections, users will also need a way to trigger the chip into download mode. This is accom- plished via pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 46. To get the ADuC812 ...
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... The only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure. Typical System Configuration A typical ADuC812 configuration is shown in Figure 46. It sum- marizes some of the hardware considerations discussed in the previous paragraphs. QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC812 ...
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... For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V /V level occurs for Port 0, ALE, PSEN outputs = 100 pF LOAD 4 ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12. DV – 0.5V DD 0.2V TEST POINTS 0.2V 0.45V ( 3 5.0 V 10% ...
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... Variable Clock Min Max 2t – – – – 100 CK t – – – 105 – – 105 LLIV t PLIV t PXIZ t PXIX INSTRUCTION (IN) t PHAX ADuC812 Unit ...
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... ADuC812 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX Data Float after RD t RHDZ t ALE Low to Valid Data In ...
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... LLWL WLWH t AVWL t QVWX t LLAX t AVLL QVWH A0–A7 DATA A16–A23 A8–A15 Figure 53. External Data Memory Write Cycle –49– ADuC812 Variable Clock Min Max Unit 6t – 100 – – – ...
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... ADuC812 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock XHQX ALE (O) TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) ...
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... CONDITION CONDITION REV SUP MSB LSB t SU; DAT t HD; DAT HD; STA t HIGH 1 2– SUP LOW 2 Figure 55 Compatible Interface Timing –51– ADuC812 Min Max Unit 1.3 µs 0.6 µs 0.6 µs 100 µs 0 0.9 µs 0.6 µs 0.6 µs 1.3 µs 300 ns 300 ns 50 ...
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... ADuC812 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth LOW t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge DHD t Data Output Fall Time ...
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... MSB IN t DSU REV. E Min 100 100 DAV MSB BIT 6–1 BIT 6–1 t DHD Figure 57. SPI Master Mode Timing (CPHA = 0) –53– ADuC812 Typ Max Unit 330 ns 330 150 ...
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... ADuC812 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... MOSI t DSU REV. E Min 0 100 100 DAV MSB BIT 6–1 BIT 6–1 t DHD Figure 59. SPI Slave Mode Timing (CPHA = 0) –55– ADuC812 Typ Max Unit ns 330 ns 330 ...
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... ADuC812 1.03 0.88 0.73 SEATING PLANE VIEW A 0.23 0.11 BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 2.45 13.65 MAX 39 40 7.80 TOP VIEW REF (PINS DOWN) PIN 0.65 BSC 2.10 7 2.00 0 1.95 0.10 MIN COPLANARITY VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MO-022-AC-1 ...
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... Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to Figure Edits to SERIAL PERIPHERAL INTERFACE Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Edits to TABLE Edits to TABLE XXIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Edits to TABLES XXIV, XXV, and XXVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10/01—Data Sheet changed from REV REV. B. Entire Data Sheet Revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All REV. E –57– ADuC812 Page ...
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