ADP320 Analog Devices, ADP320 Datasheet - Page 16

• Manufacturer Part Number: ADP320
• Description: Triple, 200 mA, Low Noise, High PSRR Voltage Regulator
• Manufacturer: Analog Devices

ADP320
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
where:
C
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed
to be 15% for an X5R dielectric. TOL is assumed to be 10%,
and C
Substituting these values into Equation 1 yields
Therefore, the capacitor chosen in this example meets the mini-
mum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP320 triple LDO, it is
imperative that the effects of dc bias, temperature, and toler-
ances on the behavior of the capacitors are evaluated for each
application.
UNDERVOLTAGE LOCKOUT
The ADP320 triple LDO has an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage bias, VBIAS, is less than approximately 2.2 V. This
ensures that the inputs of the ADP320 triple LDO and the
output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP320 triple LDO uses the ENx pins to enable and
disable the VOUTx pins under normal operating conditions.
Figure 44 shows a rising voltage on EN crossing the active
threshold, then VOUTx turns on. When a falling voltage on
ENx crosses the inactive threshold, VOUTx turns off.
BIAS
C
C
is the effective capacitance at the operating voltage.
BIAS
EFF
EFF
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
is 0.94 μF at 1.8 V from the graph in Figure 43.
= C
= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
0.4
BIAS
0.5
× (1 − TEMPCO) × (1 − TOL)
Figure 44. Typical ENx Pin Operation
0.6
ENABLE VOLTAGE (V)
0.7
0.8
0.9
V
OUT
1.0
@ 4.5V
IN
1.1
1.2
Rev. A | Page 16 of 20
(1)
As shown in Figure 44, the ENx pin has built-in hysteresis.
This prevents on/off oscillations that can occur due to noise
on the ENx pin as it passes through the threshold points.
The active/inactive thresholds of the ENx pin are derived
from the V
changing input voltage. Figure 45 shows typical ENx active/
inactive thresholds when the input voltage varies from 2.5 V
to 5.5 V.
The ADP320 triple LDO utilizes an internal soft start to limit
the inrush current when the output is enabled. The start-up
time for the 2.8 V option is approximately 220 µs from the time
the ENx active threshold is crossed to when the output reaches
90% of its final value. The start-up time is somewhat dependent
on the output voltage setting and increases slightly as the output
voltage increases.
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1
2
CH1 1V
CH3
2.5
Figure 45. Typical ENx Pins Thresholds vs. Input Voltage
BIAS
500mV
CH1 = V
V
voltage. Therefore, these thresholds vary with
EN
V
EN
3.0
B
B
Figure 46. Typical Start-Up Time,
EN
W
W
RISE
I
LOAD1
, CH2 = V
CH4 500mV
CH2
= I
3.5
LOAD2
INPUT VOLTAGE (V)
500mV
OUT1
= I
, CH3 = V
B
B
LOAD3
4.0
W
W
M100µs A CH1
= 100 mA,
T
10.2%
OUT2
V
V
V
4.5
OUT1
OUT2
OUT3
, CH4 = V
V
EN
5.0
OUT3
FALL
540mV
5.5