ADP1864 Analog Devices, ADP1864 Datasheet - Page 5

• Manufacturer Part Number: ADP1864
• Description: Constant Frequency Current-Mode Step-Down DC-to-DC Controller in TSOT
• Manufacturer: Analog Devices

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
COMP
GND
FB
CS
IN
PGATE
Description
Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a
series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between
COMP and GND to further reduce switching jitter. The value of this is typically one-tenth of the main compensation
capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET.
Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog
GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND
pin. See the Layout Considerations section for more information.
Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The
regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin.
Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal
used to terminate the PWM on time. Place a current sense resistor between IN and CS to set the current limit. The
current limit threshold is typically 125 mV.
Power Input. IN is the power supply to the ADP1864 and the positive input of the current sense amplifier. Connect
IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor as close as possible
to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin.
Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the
external MOSFET.
COMP
GND
FB
Figure 2. Pin Configuration
Rev. B | Page 5 of 16
1
2
3
(Not to Scale)
ADP1864
TOP VIEW
5
4
6
PGATE
IN
CS
ADP1864