TDA7442D STMicroelectronics, TDA7442D Datasheet
![IC PROCESSOR TONE/SURRND 28-SOIC](/photos/6/56/65690/stmicroelectronics-28-soic_sml.jpg)
TDA7442D
Specifications of TDA7442D
Available stocks
Related parts for TDA7442D
TDA7442D Summary of contents
Page 1
... V S L-IN3 23 CREF L-IN4 22 SDA MUXOUT(L) 21 SCL IN(L) 20 DIG-GND MUXOUT(R) 19 TREBLE(R) N.C. 18 TREBLE(L) IN(R) 17 PS1 BIN( BOUT(R) 15 BOUT(L) BIN(L) TDA7442 TDA7442D SO-28 SDIP-32 Package SDIP-32 SO-28 Tape & Reel 1 32 R-IN3 2 31 R-IN4 3 30 L-OUT 4 29 R-OUT 5 28 AGND CREF 8 25 ...
Page 2
... L-IN3 50K 0. L-IN4 + + L+R 50K 0. R-IN1 50K 0. R-IN2 50K 0. R-IN3 30K 50K 0. R-IN4 31.5dB 50K control MONITOR(R) MUXOUT(R) 2.2 F Figure 4. Block Diagram (TDA7442D) 2.2 F MUXOUT(L) 0.47 F 31.5dB control L-IN1 50K 0. 30K L-IN2 50K 0. L-IN3 50K 0. L-IN4 + + L+R 50K 0. R-IN1 50K 0. R-IN2 50K 0 ...
Page 3
... Step Resolution STEP R Internal Feedback Resistance B Parameter = 1Vrms (mode = OFF) out ) , Parameter Parameter = 9V 10K , Test Condition , Mode = OFF out THD = 0.3% Max. Boost/cut TDA7442 - TDA7442D Min. Typ. Max 10.2 2 0.01 0.1 106 90 -14 +14 -14 +14 -79 0 100 Value Max. 85 Value 11 - -55 to +150 = 1Vrms; R ...
Page 4
... TDA7442 - TDA7442D Table 5. Electrical Characteristics (continued) Refer to the test circuit T = 25°C, V amb 0dB), Effect Ctrl = -6dB, MODE = OFF 1KHz unless otherwise specified. Symbol Parameter TREBLE CONTROL G Control Range t T Step Resolution STEP EFFECT CONTROL C Control Range RANGE S Step Resolution STEP ...
Page 5
... DC Voltage Level OUT BUS INPUTS V Input Low Voltage IL V Input High Voltage IH I Input Current IN V Output Voltage SDA O Acknowledge = 9V 10K , V = 1Vrms Test Condition 1Vrms 0. 1.6mA O TDA7442 - TDA7442D = 600 , all controls flat ( Min. Typ. Max. Unit 3.8 V 0.01 0 2.5 Vrms 4 0.4 ...
Page 6
... TDA7442 - TDA7442D BUS INTERFACE Data transmission from microprocessor to the TDA7442D and vice versa takes place through the 2 wires BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW ...
Page 7
... D95AU306 4.1.2 Incremental Bus The TDA7442D receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (in- cremental bus): now loop condition with an autoincrease of the subaddress whereas SUBAD- DRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition ...
Page 8
... TDA7442 - TDA7442D 5 DATA BYTES Address = 80(HEX) 5.1 Function Selection: The first byte (subaddress) MSB incremental bus; active incremental bus indifferent 0,1 Input Attenuation Selection MSB INPUT ATTENUATION = 0 ~ -31.5dB 8/ LSB SUBADDRESS D0 0 INPUT ATTENUATION 1 SURROUND & OUT & EFFECT CONTROL 0 PHASE RESISTOR ...
Page 9
... Surround Selection MSB PHASE RESISTOR SELECTION MSB BASS SELECTION MSB TDA7442 - TDA7442D LSB D0 SURROUND MODE 0 SIMULATED STEREO 1 MUSIC 0 OFF OUT VAR FIX EFFECT CONTROL - -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 LSB SURROUND PHASE RESISTOR D0 PHASE SHIFT LSB BASS STEPS 0 -14 1 - 9/17 ...
Page 10
... TDA7442 - TDA7442D 5.2 Surround Selection (continued) MSB SPEAKER SELECTION MSB INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB TREBLE SELECTION MSB 10/ LSB BASS STEPS LSB SPEAKER/ATT STEPS STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE LSB TREBLE STEPS 0 -14 0 - ...
Page 11
... INPUT SELECTION MSB INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB TREBLE SELECTION MSB INPUT SELECTION MSB TDA7442 - TDA7442D LSB TREBLE STEPS LSB D0 INPUT MULTIPLEXER 0 IN2 0 IN3 0 IN4 0 IN1 LSB TREBLE STEPS 0 -14 0 - LSB D0 INPUT MULTIPLEXER 0 IN2 0 IN3 0 IN4 0 IN1 11/17 ...
Page 12
... TDA7442 - TDA7442D Table 6. POWER ON RESET BASS TREBLE SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER ATTENUATION L &R INPUT ATTENUATION INPUT Figure 8. PIN: TREBLE-L, TREBLE 25K GND D95AU309 Figure 9. PIN: VOUT REF GND 10K GND Figure 10. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3,L-IN4, R-IN4, ...
Page 13
... Figure 15. PIN: BASS-LI, BASS- 45K : Bass GND BASS-LO BASS-RO Figure 16. PIN: BASS-LO, BASS- D98AU949 TDA7442 - TDA7442D V S 45K GND BASS-LI,BASS- D98AU950 13/17 ...
Page 14
... TDA7442 - TDA7442D Figure 17. SO-28 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. MAX. A 2.65 a1 0.1 0.3 b 0.35 0.49 b1 0.23 0. (typ.) D 17.7 18 10.65 e 1.27 e3 16.51 F 7.4 7.6 L 0.4 1. (max.) 14/17 inch MIN. TYP. MAX. 0.104 0.004 0.012 0.014 0.019 0.009 ...
Page 15
... Plastic Dip 32L) 0.1 0.12 0. TDA7442 - TDA7442D OUTLINE AND MECHANICAL DATA SDIP- SDIP32M 0123183 15/17 ...
Page 16
... TDA7442 - TDA7442D Table 7. Revision History Date Revision January 2001 June 2004 16/17 1 First issue. 2 Changed the Style-sheet in compliance to the new “Corporate Technical Pubblications Design Guide” Description of Changes ...
Page 17
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES www.st.com TDA7442 - TDA7442D 17/17 ...