LPC2470 NXP Semiconductors, LPC2470 Datasheet
LPC2470
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LPC2470 Summary of contents
Page 1
... Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units, and up to 160 fast GPIO lines. The LPC2470 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC), allowing the external inputs to generate edge-triggered interrupts ...
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... C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... Portable electronics Point-of-Sale (POS) equipment 4. Ordering information Table 1. Ordering information Type number Package Name LPC2470FBD208 LQFP208 LPC2470FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2470FBD208 n ...
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... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2470 block diagram LPC2470 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB TEST/DEBUG SRAM INTERFACE INTERNAL ARM7TDMI-S ...
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... LPC2470 pinning TFBGA208 package Pin Symbol V 3 P1[0]/ENET_TXD0 SSIO P1[9]/ENET_RXD0 7 P1[14]/ENET_RX_ER P1[3]/ENET_TXD3/ 11 P4[15]/A15 MCICMD/PWM0[2] All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 156 ...
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... LCDVD[1]/TD2/CAP2[1] LCDVD[2]/TXD3 P3[18]/D18/ 16 P4[12]/A12 PWM0[3]/CTS1 - - TDO 4 P3[12]/D12 V 8 P3[8]/D8 DD(3V3 DD(DCDC)(3V3) SSCORE P2[2]/PWM1[3]/CTS1/ 16 P1[13]/ENET_RX_DV PIPESTAT1/LCDDCLK - - TMS 4 P3[3]/D3 P2[3]/PWM1[4]/DCD1/ 17 P2[6]/PCAP1[0]/RI1/ PIPESTAT2/LCDFP TRACEPKT1/ LCDVD[0]/LCDVD[4] P3[29]/D29/ 4 DBGEN MAT1[0]/PWM1[6] LPC2470 © NXP B.V. 2011. All rights reserved ...
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... SSCORE V 17 P0[17]/CTS1/ DD(3V3) MISO0/MISO V 4 P2[30]/DQMOUT2/ SSIO MAT3[2]/SDA2 P4[7]/A7 17 P0[19]/DSR1/ MCICLK/SDA1 VBAT 4 XTAL1 P0[21]/RI1/ 17 P0[20]/DTR1/ MCIPWR/RD1 MCICMD/SCL1 P2[29]/DQMOUT1 4 XTAL2 V 17 P0[22]/RTS1/ SSIO MCIDAT0/TD1 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 MAT3[1]/MOSI0 P1[18]/USB_UP_LED1 DD(3V3) PWM1[1]/CAP1[0] LPC2470 © NXP B.V. 2011. All rights reserved ...
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... MAT3[0]/MISO0 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 USB_CONNECT2/ SSEL1 P4[2]/A2 12 P1[27]/USB_INT1/ LCDVD[13]/LCDVD[21]/ USB_OVRCR1/CAP0[1] P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ MAT3[0] LCDVD[5]/LCDVD[9]/ LCDVD[19]/MCIDAT3/ I2STX_SDA - - P2[18]/CLKOUT0 4 P0[29]/USB_D+1 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ LCDVD[6]/LCDVD[10]/ LCDVD[8]/LCDVD[12]/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 P0[0]/RD1/TXD3/SDA1 16 P4[3]/ LPC2470 © NXP B.V. 2011. All rights reserved ...
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... O LCDVD[8] — LCD data. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 2 S-bus [2] [2] 2 S-bus [2] © NXP B.V. 2011. All rights reserved. ...
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... HIGH (flashes) when host is enabled and detects activity on the bus. I/O MOSI1 — Master Out Slave In for SSP1. I AD0[7] — A/D converter 0, input 7. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 2 S-bus [2] [2] 2 ...
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... RTS1 — Request to Send output for UART1. I/O MCIDAT0 — Data line 0 for SD/MMC interface. O TD1 — CAN1 transmitter output. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... ENET_TXD2 — Ethernet transmit data 2 (MII interface). O MCICLK — Clock output line for SD/MMC interface. O PWM0[1] — Pulse Width Modulator 0, output 1. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 2 S-bus specification. 2 S-bus 2 S-bus specification ...
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... P1[15] — General purpose digital input/output pin. I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/ Ethernet Receive Clock (MII interface). All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... LCDVD[9]/LCDVD[13] — LCD data. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [7] [7] [7] [7] © NXP B.V. 2011. All rights reserved. ...
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... USB_OVRCR2 — Over-Current status for USB port 2. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [7] [7] [7] [ serial clock (OTG transceiver). ...
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... PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACEPKT1 — Trace Packet, bit 1. O LCDVD[0]/LCDVD[4] — LCD data. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [8] [8] [8] [8] [8] [8] [8] ...
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... MCIDAT3 — Data line 3 for SD/MMC interface. I/O I2STX_SDA — Transmit data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [8] [8] [8] [8] ...
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... CKEOUT3 — SDRAM clock enable 3. O MAT3[1] — Match output for Timer 3, channel 1. I/O MOSI0 — Master Out Slave In for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... D11 — External memory data line 11. [1] I/O P3[12] — General purpose digital input/output pin. I/O D12 — External memory data line 12. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... D22 — External memory data line 22. I PCAP0[0] — Capture input for PWM0, channel 0. I RI1 — Ring Indicator input for UART1. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... The operation of port 4 pins depends upon the pin function selected via the pin connect block. [1] I/O P4[0] — ]General purpose digital input/output pin. I/O A0 — External memory address line 0. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... A18 — External memory address line 18. [1] I/O P4[19] — General purpose digital input/output pin. I/O A19 — External memory address line 19. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. I/O USB_D2 — USB port 2 bidirectional D line. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [11] [11] [11] [11] © ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2470 being in Reset state. [12] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller 20, and Table 21. 19, Table 20, and Table 21. Table 20, and Table 21. Table 19, Table 20, and Table 19, Table 20, and LPC2470 DD(3V3 lines. Open-drain Table 21. Table 21. © NXP B.V. 2011. All rights reserved ...
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... AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2470 implements two AHBs in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...
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... ARM code while retaining most of the ARM’s performance. 7.2 On-chip SRAM The LPC2470 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. ...
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... EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB SPECIAL REGISTERS RESERVED ADDRESS SPACE 0.0 GB LPC2470 memory map All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller BOOT ROM 002aad316 LPC2470 0xFFFF FFFF ...
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... External memory controller The LPC2470 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...
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... Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2470 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC2470 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...
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... LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. LPC2470 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2470 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2470 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. LPC2470 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 2 C interface © NXP B.V. 2011. All rights reserved ...
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... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2470 to generate a variable analog output. The maximum output value of the DAC is V 7.14.1 Features • 10-bit DAC • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2470 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2470 supports bit rates up to 400 kbit/s (Fast I 7.19.1 Features • standard I • ...
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... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2470 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2470. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down and Deep power-down modes. On the LPC2470, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3 ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2470 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2470 begins operation at power-up and when awakened from Power-down and Deep-power down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...
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... NXP Semiconductors 7.25.4 Power control The LPC2470 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...
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... Battery RAM, as long as the external power to the VBAT pin is maintained. 7.25.4.5 Power domains The LPC2470 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2470, I/O pads are powered by the 3 ...
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... VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2470 when the voltage on the V DD(DCDC)(3V3) below which point the power-on reset circuitry maintains the overall Reset. ...
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... Once booting is over the application must map interrupt vectors to the proper domain. 7.27 Emulation and debugging The LPC2470 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2470 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4 ...
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... JEDEC (4.5 in 4 in) 0 m/s 1 m/s 2.5 m/s 8-layer (4.5 in 3 in) 0 m/s 1 m/s 2.5 m/s jc jb All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller (C), can be calculated using the following j and V . The I/O power dissipation Min Typ Max - ...
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... DD(3V3) no pull-up/down (0.5V ) < V < DD(3V3) I (1.5V ); DD(3V3) < 125 [5][6][7] pin configured to provide a [8] digital function output active All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3.3 V DDA - 17.4 ...
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... V OL DDA < V < DD(3V3 OLS DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [1] Min Typ Max - - 0.8 0 [ DD(3V3) 0.4 [ 0.4 4 [9] - ...
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... GND with 33 series resistor; steady state drive drops below 1 i(VBAT) amb is grounded. DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [1] Min Typ Max 0.5 +1.8 +1.95 0.5 +1.8 +1.95 0.5 +1.8 +1.95 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller V = 3.3 V DD(3V3 3.0 V DD(3V3 temperature (° C. versus temperature in Power-down mode DD(IO temperature (° C. amb versus temperature in Power-down BAT LPC2470 002aae049 85 002aae050 85 © NXP B.V. 2011. All rights reserved ...
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... 3 DD(3V3) DD(DCDC)(3V3) amb I/O maximum supply current I DD(IO) mode All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 002aae051 35 60 temperature (°C) at different temperatures DD(DCDC)pd(3V3) 002aae046 35 60 temperature (° C. ...
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... Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller temperature (° C amb versus temperature in Deep BAT temperature (°C) DD(DCDC)dpd(3V3) LPC2470 002aae047 85 002aae048 85 versus © NXP B.V. 2011. All rights reserved ...
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... 0.2 Conditions 3.3 V; standard port pins. DD(3V3) All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 002aaf112 16 I (mA) OH versus HIGH-level output source current OH 002aaf111 °C 25 °C −40 °C 0.4 ...
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... SPI Master mode; see Figure CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [1] [2] Min Typ Max 1000 0 cy(clk) 0.4 ...
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... Figure 16 see Figure must reject as EOP; see Figure 16 must accept as EOP; see Figure 16 All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller [2] Min Typ Max 3.96 4.02 4.04 - 32.768 - Min Typ Max 3 ...
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Static external memory interface Table 14. Dynamic characteristics: Static external memory interface = 40 pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS ...
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Table 14. Dynamic characteristics: Static external memory interface = 40 pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH to address BLSHANV ...
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... See Figure 18. LPC2470 Product data sheet = 3.6 V, EMC Dynamic Read Config Register = 0x0 DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Min Typ Max [1] - 1.05 1.76 [1] 0.1 1. ...
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... T [1] [1] - [1] 2 [1] 2 [1] [1] - 3 [1] All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Typ Max 1 cy(CCLK) cy(CCLK) cy(CCLK) 1 cy(CCLK) 2 cy(CCLK) cy(CCLK) ...
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... OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aad956 © NXP B.V. 2011. All rights reserved. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller extended source EOP width: t receiver EOP width: t sampling edges 002aad326 t h(XXX su(D) h(D) LPC2470 FEOPT , t EOPR1 EOPR2 002aab561 002aad636 © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller Min Typ [1][2][ [1][ [1][ [1][ [1][ [ 19. LPC2470 Max Unit V V DDA 1 pF 1 LSB 2 LSB 3 LSB 0.5 % 4 LSB 40 k Figure 19. © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller (1) 1018 1019 1020 1021 1022 1023 − i(VREF) SSA 1 LSB = 1024 LPC2470 offset gain error error 1024 002aae604 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors AD0[y] Fig 20. Suggested ADC interface - LPC2470 AD0[y] pin LPC2470 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller R vsi ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Min Typ Max 200 - Color STN single panel LCD function LPC2470 pin used - - - - - - - - - - - - - - - - - - - - - - - - - ...
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... P1[20] [2] - P2[13] [2] - P2[12] [1] UD[3] P2[9] [1] UD[2] P2[8] [1] UD[1] P2[7] All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Color STN single panel LCD function LPC2470 pin used [1] LCDLP P2[5] [1] LCDENAB/ P2[4] LCDM [1] LCDFP P2[3] [1] LCDDCLK P2[2] [1] LCDLE P2[1] [1] LCDPWR P2[0] [2] LCDCLKIN P2[0] Color STN dual panel ...
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... LCDVD[11 LCDVD[10 LCDVD[ LCDVD[ [1] LCDVD[7] P2[9] RED3 [1] LCDVD[6] P2[8] RED2 [1] LCDVD[5] P2[7] RED1 [1] LCDVD[4] P2[6] RED0 LCDVD[ LPC2470 Product data sheet 8-bit mono STN dual panel LCD function LPC2470 pin used [1] UD[0] P2[6] [1] LCDLP P2[5] [1] LCDENAB/ P2[4] LCDM [1] LCDFP P2[3] [1] LCDDCLK P2[2] [1] LCDLE P2[1] [1] LCDPWR P2[0] [2] LCDCLKIN P2[11] LPC2470 LCD pin used function [4] P1[29] ...
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... CS1 OE BLS1 D[15:8] A[a_b:1] Fig 21. Booting from two 8-bit memory chips LPC2470 Product data sheet TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC2470 LCD LPC2470 pin pin used function used - - P4[28 ...
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... NXP Semiconductors Fig 22. Booting from a single 16-bit memory chip 14.3 Suggested USB interface solutions LPC24XX Fig 23. LPC2470 USB interface on a self-powered device LPC2470 Product data sheet CS1 16-bit BLS1 MEMORY LB BLS0 IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ ...
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... NXP Semiconductors LPC24XX Fig 24. LPC2470 USB interface on a bus-powered device LPC2470 Product data sheet V DD(3V3 USB_UP_LED 1.5 kΩ V BUS Ω USB_D Ω USB_D− SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 ...
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... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 25. LPC2470 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2470 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 26. LPC2470 USB OTG port configuration: VP_VM mode LPC2470 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 27. LPC2470 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2470 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526 ...
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... USB_D+2 USB_D−2 USB_UP_LED2 Fig 28. LPC2470 USB OTG port configuration: USB port 1 host, USB port 2 host 14.4 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... X2 Maximum crystal series resistance < 300 < 300 < 300 < 300 < 200 < 100 < 160 < 60 < 80 LPC2470 Figure 30 and in and 002aag469 External load capacitors ...
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... R S 002aaf495 evaluation Figure 31. Since the feedback resistance is and C need to be connected the typical load L and C X1 External load capacitors LPC2470 , Table 24 specified Parasitics L /C components © NXP B.V. 2011. All rights reserved. ...
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... Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller , and C should be chosen smaller weak pull-up pull-up enable weak pull-down select analog input LPC2470 , and C in case ESD PIN ESD V SS 002aaf496 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 14.8 Reset pin configuration Fig 33. Reset pin configuration LPC2470 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller ESD ESD V SS 002aaf274 © ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION LPC2470 SOT459 θ θ 1. 1.08 0 ISSUE DATE 00-02-06 03-02-20 © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 Flashless 16-bit/32-bit microcontroller detail 0.08 0.12 0.1 EUROPEAN PROJECTION LPC2470 SOT950 ISSUE DATE 06-06-01 06-06-14 © NXP B.V. 2011. All rights reserved ...
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... Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 17. Revision history Table 26. Revision history Document ID Release date LPC2470 v.4 20110908 • Modifications: Table 4 “Pin • Table 6 “Limiting • Table 6 “Limiting • Table 8 “Thermal resistance value (C/W): ±15 • Table 14 “Dynamic characteristics: Static external memory = 1 MHz”. • Table 14 “Dynamic characteristics: Static external memory values for t • ...
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... All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller Change notice Supersedes - LPC2470 v DD(DCDC)pd(3V3) DD(DCDC)dpd(3V3) 2 typ for I C-bus pins from 0.5V hys DD - LPC2470 v.1 . DD(DCDC)act(3V3 DD(3V3) DD(DCDC)(3V3 © NXP B.V. 2011. All rights reserved. , and to 0.05V . ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...
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... Electrical pin characteristics Dynamic characteristics 11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 59 11.2 I/O pins 11.3 USB interface All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 September 2011 LPC2470 Flashless 16-bit/32-bit microcontroller 2 C-bus serial I/O controller . . . . . . . . . . . . . . 38 2 S-bus serial I/O controllers . . . . . . . . . . . . . 38 © NXP B.V. 2011. All rights reserved. continued >> ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2470 All rights reserved. Date of release: 8 September 2011 Document identifier: LPC2470 ...