MAX9041AESA+ Maxim Integrated Products, MAX9041AESA+ Datasheet - Page 10
![IC COMPARATOR SNGL 8-SOIC](/photos/1/39/13902/8-soic_21-0042b_sml.jpg)
MAX9041AESA+
Manufacturer Part Number
MAX9041AESA+
Description
IC COMPARATOR SNGL 8-SOIC
Manufacturer
Maxim Integrated Products
Type
with Voltage Referencer
Datasheet
1.MAX9050AEUKT.pdf
(20 pages)
Specifications of MAX9041AESA+
Number Of Elements
1
Output Type
CMOS, Push-Pull, Rail-to-Rail, TTL
Voltage - Supply
2.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3) In this example, let V
4) Select R2. In this example, we will choose 1kΩ.
5) Select V
6) Solve for R1:
where R1 ≈ 100kΩ, V
Power-supply bypass capacitors are not typically need-
ed, but would be called for in cases where supply
impedance is high, supply leads are long, or excessive
noise is expected on the supply lines. Use 100nF
bypass capacitors under these conditions. Minimize
signal trace lengths to reduce stray capacitance.
The MAX9039/MAX904_/MAX905_ do not require an
output capacitor on REF for frequency stability. They
are stable for capacitive loads up to 4.7nF. However, in
applications where the load or the supply can experi-
ence step changes, an output capacitor will reduce the
Micropower, Single-Supply, UCSP/SOT23
Comparator + Precision Reference ICs
Figure 2. Time Averaging of the Input Signal for Data Recovery
10
and
V
IN
______________________________________________________________________________________
Reference Output/Load Capacitance
HYS
10kΩ
0.1μF
. In this example, we will choose 50mV.
V
V
TH
TL
V
0 050
HYS
Board Layout and Bypassing
=
.
=
2 5 2 5
TH
2 5 1
IN+
IN-
.
.
=
CC
=
= 2.525V, and V
+
⎛
⎜
⎝
V
5
CC
= 5V and V
−
⎛
⎜
⎝
.
R
R
⎛
⎜
⎝
⎛
⎜
⎝
1 1000
1000
1
R
R
+
R
1
+
1
2
V
R
R
V
+
R
+
CC
2
EE
2
2
V
R
R
CC
2
⎞
⎟
⎠
MAX9039–MAX9043
MAX9050–MAX9053
2
⎞
⎟
⎠
⎞
⎟
⎠
⎞
⎟
⎠
REF
TL
= 2.5V:
= 2.475V.
OUT
amount of overshoot (or undershoot) and assist the cir-
cuit’s transient response. When an application is not
subject to transient conditions, the REF capacitor can
be omitted.
Digital data is often embedded into a bandwidth- and
amplitude-limited analog path. Recovering the data can
be difficult. Figure 2 compares the input signal to a
time-averaged version of itself. This self-biases the
threshold to the average input voltage for optimal noise
margin.
Even severe phase distortion is eliminated from the dig-
ital output signal. Be sure to choose R1 and C1 so that:
where f
digital data stream.
For general UCSP package information and PC layout
considerations, please refer to Maxim Application
Note,"Wafer-Level Chip-Scale Package."
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP. UCSPs are attached through direct
solder contact to the user’s PC board, foregoing the
inherent stress relief of a packaged product lead frame.
Solder joint contact integrity must be considered.
Information on Maxim’s qualification plan, test data,
and recommendations are detailed in the UCSP appli-
cation note, which can be found on Maxim’s website at
www.maxim-ic.com.
PROCESS: BiPOLAR
CAR
is the fundamental carrier frequency of the
f
CAR
UCSP Package Consideration
>>
Biasing for Data Recovery
2 R1C1
π
1
Chip Information
UCSP Reliability