MAX975ESA+ Maxim Integrated Products, MAX975ESA+ Datasheet - Page 13

IC COMPARATOR SNGL 3V/5V 8-SOIC

MAX975ESA+

Manufacturer Part Number
MAX975ESA+
Description
IC COMPARATOR SNGL 3V/5V 8-SOIC
Manufacturer
Maxim Integrated Products
Type
General Purposer
Datasheet

Specifications of MAX975ESA+

Number Of Elements
1
Output Type
CMOS, Rail-to-Rail, TTL
Voltage - Supply
2.7 V ~ 5.25 V
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Number Of Channels
1 Channel
Product
Digital Comparators
Offset Voltage (max)
+/- 5 mV
Input Bias Current (max)
- 300 nA
Supply Voltage (max)
5.25 V
Supply Voltage (min)
2.7 V
Supply Current (max)
500 uA
Maximum Power Dissipation
471 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
STAT’s function is to indicate the comparator’s operat-
ing mode. When STAT is low, the comparator is in high-
speed mode and will meet the guaranteed propagation
delay. When STAT is high, the comparator is in auto-
standby mode, in low-power mode, or in transition to
high-speed mode. An additional feature of this pin is
that it can source 3mA of current. When STAT is high,
additional circuitry can be powered. This circuitry can
be automatically powered up or powered down,
depending on the input signal or lack of input signal
received by the MAX975/MAX977.
The charge currents for the capacitor connected to
STO_ are on the order of 100nA. This necessitates cau-
tion in capacitor type selection and board layout.
Capacitor leakage currents must be less than 1nA to
prevent timing errors. Ceramic capacitors are available
in values up to 1µF, and are an excellent choice for this
application. If a larger capacitance value is needed,
use parallel ceramic capacitors to get the required
capacitance. Aluminum and tantalum electrolytic
capacitors are not recommended due to their higher
leakage currents.
Board layout can create timing errors due to parasitic
effects. Make the STO_ traces as short as possible to
reduce capacitance and coupling effects. When driving
STO_ to disable auto-standby mode, use standard
CMOS logic isolated with a low-leakage (<1nA) diode,
such as National’s FJT1100 (Figure 3). 15nA leakage
typically results in 10% error.
The MAX977 has separate timing inputs (STOA and
STOB). These pins must have separate capacitors. The
timing circuits will not operate correctly if a single
capacitor is used with STOA and STOB connected
together.
The relationship between the timeout period and the
STO_ capacitor is t
is in pF. This equation is for larger capacitance values,
and does not take into account variations due to board
capacitance and board leakage. If less than 1ms is
desired, subtract the ~3pF STO_ parasitic capacitance
from the calculated value.
The MAX975/MAX977’s high gain bandwidth requires
design precautions to realize the comparator’s full high-
speed capability. The following precautions are recom-
mended:
__________Applications Information
Powering Circuitry with STAT
Circuit Layout and Bypassing
______________________________________________________________________________________
ASB
= 10 x C
STO_ Considerations
STO
_ s, where C
Single/Dual, +3V/+5V Dual-Speed
Comparators with Auto-Standby
STO
_
1) Use a printed circuit board with an unbroken, low-
2) Place a decoupling capacitor (a 0.1µF ceramic
3) Keep lead lengths short on the inputs and outputs, to
4) Solder the devices directly to the printed circuit
5) Minimize input impedance.
6) For slowly varying inputs, use a small capacitor
Figure 4 shows an application using the MAX975 as an
infrared receiver. The infrared photodiode creates a
current relative to the amount of infrared light present.
This current creates a voltage across R
voltage level crosses the voltage applied by the voltage
divider to the inverting input, the output transitions. If
the photodiode is not receiving enough signal to cause
transitions on the MAX975’s output, STAT is used as a
loss-of-signal indicator. R3 adds additional hysteresis
for noise immunity.
Figure 3. Driving STO
Figure 4. IR Receiver
inductance ground plane.
capacitor is a good choice) as close to V
sible.
avoid unwanted parasitic feedback around the com-
parators.
board instead of using a socket.
(~1000pF) across the inputs to improve stability.
V
CC
CMOS
LOGIC
V
CC
R1
R
D
_
with CMOS Logic
R2
R3
GND
V
V
CC
CC
STAT
STO_
MAX975
IR Receiver
OUT
LOSS OF SIGNAL
D
. When this
CC
as pos-
13

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