MCP6564T-E/ST Microchip Technology, MCP6564T-E/ST Datasheet - Page 15

• Manufacturer Part Number: MCP6564T-E/ST
• Description: IC COMP QUAD 1.8V PP 14-TSSOP
• Manufacturer: Microchip Technology
• Type: General Purposer

Specifications of MCP6564T-E/ST

• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Number Of Elements: 4
• Output Type: CMOS, Push-Pull, Rail-to-Rail, TTL
• Voltage - Supply: 1.8 V ~ 5.5 V
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP6564T-E/STTR

4.0
The MCP6561/1R/1U/2/4 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of high speed applications requiring low power
consumption.
4.1
4.1.1
The input stage of this family of devices uses three
differential input stages in parallel: one operates at low
input voltages, one at high input voltages, and one at
mid input voltage. With this topology, the input voltage
range is 0.3V above V
providing low offset voltage through out the common
mode range. The input offset voltage is measured at
both V
operation.
The MCP6561/1R/1U/2/4 family has internally-set
hysteresis
offset accuracy and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage
offset voltage (V
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (V
the same trip points.
FIGURE 4-1:
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
© 2009 Microchip Technology Inc.
-1
-2
-3
8
7
6
5
4
3
2
1
0
SS
E
V
APPLICATIONS INFORMATION
Comparator Inputs
NI
DD
- 0.3V and V
V
.
NORMAL OPERATION
HYST
= 5.0V
V
Figure 4-1
OUT
that is small enough to maintain input
OS
) is the center (average) of the
Time (100 ms/div)
HYST
The MCP6561/1R/1U/2/4
DD
DD
depicts this behavior. Input
) is the difference between
and 0.3V below V
+ 0.3V to ensure proper
Hysteresis
V
IN
–
SS
, while
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V
Maximum Ratings* at the beginning of Section 1.0
“Electrical Characteristics”).
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
and V
resistors R
of the input pin. Diodes D
(V
implemented as shown, resistors R
the current through D
FIGURE 4-3:
Inputs.
SS
IN
MCP6561/1R/1U/2/4
. They also clamp any voltages that go too far
+ and V
V
V
V
V
V
IN
IN
1
DD
2
SS
+
–) from going too far below ground, and the
DD
B
R
R
). The input ESD diodes clamp the inputs
Figure
1
; their breakdown voltage is high enough to
1
2
Bond
Bond
Bond
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
and R
IN
≥
R
≥
R
–) from going too far above V
1
2
D
V
V
1
SS
SS
4-2. This structure was chosen to
2
D
– (minimum expected V
– (minimum expected V
limit the possible current drawn out
2
1
Simplified Analog Input ESD
Protecting the Analog
and D
Stage
Input
1
and D
2 mA
MCP656X
2 mA
+
–
2
R
.
V
3
IN
Figure 4-3
DD
2
+ and V
prevent the input pin
1
DS22139B-page 15
Bond
and R
Pad
IN
2
1
– pins (see
shows the
2
)
V
)
DD
V
also limit
OUT
IN
. When
–
IN
+