LTC1040CSW#TR Linear Technology, LTC1040CSW#TR Datasheet - Page 7

• Manufacturer Part Number: LTC1040CSW#TR
• Description: IC COMPARATOR DUAL LOWPWR 18SOIC
• Manufacturer: Linear Technology
• Series: LTCMOS™r
• Type: General Purposer

Specifications of LTC1040CSW#TR

• Number Of Elements: 2
• Output Type: CMOS, TTL
• Voltage - Supply: 2.8 V ~ 16 V, ±2.8 V ~ 8 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Offset Voltage Error
The errors due to offset, common mode, power supply
variation, gain and temperature are all included in the
offset voltage specification. This makes it easy to compute
the error when using the LTC1040.
Example: error computation for Figure 4.
Then total worst-case error is:
Note: If source resistance exceeds 10k, bypass
capacitors should be used and the associated errors must
be included.
Pulsed Power (V
It is often desirable to use comparators with resistive
networks such as bridges. Because of the extremely low
power consumption of the LTC1040, the power consumed
by these resistive networks can far exceed that of the
device itself.
At low sample rates the LTC1040 spends most of its time
off. To take advantage of this, a pulsed power (V
is provided. V
is on and to a high impedance (open circuit) when the
comparator is off. The ON time is nominally 80 s.
Figure 5 shows the V
I
I
Assume: 2.8V V
L (ERROR)
L (ERROR)
COMPARATOR ON TIME
= (100mV • 0.001 + 0.5mV) •
% =
P-P
6mA
Tracking Error
1A
Figure 5. V
80 s
P-P
is switched to V
S
U
• 100 = 0.6%.
) Output
P-P
6V.
output circuit.
P-P
U
GND
Output Switch
9
+
V
W
OS
when the comparator
18
V
Q1 P1
+
V
17
P-P
LTC1040 • AI05
100mV
1A
P-P
U
= 6mA
) output
the network should be minimized to meet the 4 s settling
time requirement. It is not recommended that V
to drive networks with source impedances, as seen by the
inputs, of greater than 10k .
In applications where an absolute reference is required,
the V
reference. The LT1009 2.5V reference, ideal in this
application, settles in approximately 2 s (see Figure 7).
The current through R1 must be large enough to supply
the LT1009 minimum bias current ( 1mA) and the load
current, I
The V
Voltage versus Load Current curve). There are two ways
V
excessive errors: (1) ratiometric networks and (2) fast
settling references.
In a ratiometric network, the inputs are all proportional to
V
absolute value of V
It is critical that the inputs to the LTC1040 completely
settle within 4 s of the start of the comparison cycle and
that they do not change during the 80 s ON time. When
driving resistive networks with V
P-P
P-P
–
(see Figure 6). Consequently, for small changes, the
can be used to power external networks without
P-P
P-P
Figure 6. Ratiometric Network Driven by V
Figure 7. Driving Reference with V
L
output voltage is not precise (see V
output can be used to drive a fast settling
V
.
IN
+
R1
LT1009
P-P
R2
V
V
P-P
TRIP
I
does not affect accuracy.
L
OUTPUT
V
R3
IN
–
–
+
+
P-P
–
–
+
+
LTC1040
LTC1040
1/2
, capacitive loading on
1/2
LTC1040 • AI07
P-P
LTC1040
LTC1040 • AI06
Output
OUTPUT
P-P
P-P
V
P-P
P-P
be used
OUTPUT
Output
1040fa
7