LT1720IS8 Linear Technology, LT1720IS8 Datasheet - Page 19

• Manufacturer Part Number: LT1720IS8
• Description: IC COMP R-RINOUT DUAL 8-SOIC
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1720IS8

• Number Of Elements: 2
• Output Type: CMOS, Rail-to-Rail, TTL
• Voltage - Supply: 2.7 V ~ 6 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
Optional Logarithmic Pulse Stretcher
The fourth comparator of the quad LT1721 can be put to
work as a logarithmic pulse stretcher. This simple circuit
can help tremendously if you don’t have a fast enough
oscilloscope (or control circuit) to easily capture 3ns
pulse widths (or faster). When an input pulse occurs, C2
is charged up with a 180ns capture
hysteresis and 10mV offset across R3 are overcome within
the fi rst nanosecond
high. When the input pulse subsides, C2 discharges with
a 540ns time constant, keeping the comparator on until
the decay overrides the 10mV offset across R3 minus
hysteresis. Because of this exponential decay, the output
pulse width will be proportional to the logarithm of the
input pulse width. It is important to bypass the circuit’s
V
keeps the quiescent input voltage in a range where forward
leakage of the diode due to the 0.4V V
comparator is not a problem.
Neglecting some effects
the input pulse as:
where
t
t
τ
τ
V
V
V
V
P
OUT
1
2
CC
OFF
H
C
CH
= input pulse width
t
= R1 || R2 • C2
= R2 • C2
= V
OUT
= 3.5mV
well to avoid coupling into the resistive divider. R4
= V
= output pulse width
= 10mV
IN
= τ
C
– V
+ t
– τ
• R2/(R1 + R2)
2
P
• ln {V
1
FDIODE
• ln [V
CH
3
CH
, switching the comparator output
• [1 – exp (–t
/(V
4
, the output pulse is related to
CH
the capture time constant
the decay time constant
the voltage drop across R1
LT1721 hysteresis
the input pulse voltage after
the diode drop
the effective source voltage
for the charge
– V
OFF
P
2
/τ
– V
time constant. The
1
)]/(V
OL
H
/2)]
of the driving
OFF
– V
H
/2)}
(1)
For simplicity, with t
delay in turn-on due to offset and hysteresis, the equation
can be approximated by:
For example, an 8ns input pulse gives a 1.67μs output
pulse. Doubling the input pulse to 16ns lengthens the
output pulse by 0.37μs. Doubling the input pulse again
to 32ns adds another 0.37μs to the output pulse, and so
on. The rate of 0.37μs per octave falls out of the above
equation as:
There is ±0.01μs jitter
uncertainty referred to the input pulse of less than 2% (60ps
resolution on a 3ns pulse with a 60MHz oscilloscope—not
bad!). The beauty of this circuit is that it gives resolution
precisely where it’s hardest to get. The jitter is due to a
combination of the slow decay of the last few millivolts
on C2 and the 4nV/√Hz noise and 400MHz bandwidth of
the LT1721 input stage. Increasing the offset across R3
or decreasing τ
dynamic range.
The circuit topology itself is extremely fast, limited theo-
retically only by the speed of the diode, the capture time
constant τ
shows results achieved with the implementation shown,
compared to a plot of Equation (1). The low end is limited
by the delivery time of the upstream comparators. As the
input pulse width is increased, the log function is con-
strained by the asymptotic RC response but, rather than
becoming clamped, becomes time linear. Thus, for very
long input pulses the third term of Equation (1) dominates
and the circuit becomes a 3μs pulse stretcher.
2
3
4
5
So called because the very fast input pulse is “captured,” for later examination, as a charge on
the capacitor.
Assuming the input pulse slew rate at the diode is infi nite. This effective delay constant, about
0.4% of τ
LT1721, this effective delay will be 2ns.
V
equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above ground.
Output jitter increases with inputs pulse widths below ~3ns.
C
is dependent on the LT1721 output voltage and nonlinear diode characteristics. Also, the Thevenin
t
Δt
OUT
OUT
1
= τ
or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited
/octave = τ
2
1
• ln [(V
and the pulse source impedance. Figure 14
2
will decrease this jitter at the expense of
2
CH
P
• ln(2)
5
< τ
• t
in the output pulse which gives an
1
P
, and neglecting the very slight
/τ
LT1720/LT1721
1
)/(V
OFF
– V
H
/2)]
19
17201fc
(2)
(3)