EP4CE15E22C9LN Altera Corporation, EP4CE15E22C9LN Datasheet - Page 34
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EP4CE15E22C9LN
Manufacturer Part Number
EP4CE15E22C9LN
Description
IC CYCLONE IV FPGA 15K 144EQFP
Manufacturer
Altera Corporation
Series
CYCLONE® IV Er
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CE15E22C9LN
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
81
Number Of Gates
-
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP Exposed Pad
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–34
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices
Cyclone IV Device Handbook,
Volume 3
Output Duty Cycle
Notes to
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output register
to output pin
(Part 1 of 2)—Preliminary
purpose I/O pins.
strength.
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table
Parameter
Symbol
1–38:
Duty Cycle Distortion Specifications
Table 1–38
OCT Calibration Timing Specification
Table 1–39
power-up for Cyclone IV devices.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for
Cyclone IV Devices
IOE Programmable Delay
Table 1–40
core voltage devices.
t
Note to
(1) OCT calibration takes place after device configuration and before entering user mode.
OCTCAL
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Paths Affected
Table
Min
45
Symbol
lists the worst case duty cycle distortion for Cyclone IV devices.
lists the duration of calibration for series OCT with calibration at device
and
1–39:
C6
Table 1–41
Max
(1)
55
—Preliminary
Number
Setting
of
7
8
2
list the IOE programmable delay for Cyclone IV E 1.0 V
Min
45
Duration of series OCT with
calibration at device power-up
C7, I7
Offset
Min
0
0
0
Max
55
Description
(1),
(2), (3)
2.054
2.010
0.641
C8L
Fast Corner
Min
45
C8, I8L, A7
—Preliminary
1.924
1.875
0.631
I8L
Max
55
Max Offset
Chapter 1: Cyclone IV Device Datasheet
3.387
3.341
1.111
C8L
November 2011 Altera Corporation
Min
45
Slow Corner
Maximum
4.017
4.252
1.377
C9L
C9L
(1),
20
Switching Characteristics
(2)
Max
55
3.411
3.367
1.124
I8L
Unit
Units
%
µs
Unit
ns
ns
ns