EP4CGX110DF27C8N Altera Corporation, EP4CGX110DF27C8N Datasheet - Page 37
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EP4CGX110DF27C8N
Manufacturer Part Number
EP4CGX110DF27C8N
Description
IC CYCLONE IV FPGA 110K 672FBGA
Manufacturer
Altera Corporation
Series
CYCLONE® IV GXr
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CGX110DF27C8N
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5621760
Number Of I /o
393
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX110DF27C8N
Manufacturer:
ALTERA10
Quantity:
132
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices
Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices
November 2011 Altera Corporation
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software
Parameter
Parameter
Table
Table
1–44:
1–45:
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock network
I/O output
register to
pad
Pad to global
clock
network
Affected
Affected
Paths
Paths
Settings
Settings
Number
Number
12
12
of
of
7
8
2
2
Offset
Offset
Min
Min
0
0
0
0
0
0
1.314
1.313
0.461
0.712
0.438
0.713
Fast Corner
C6
Fast Corner
C6
1.210
1.208
0.421
0.682
0.404
0.682
I7
I7
(1),
2.209
2.205
0.789
1.225
0.751
1.228
C6
C6
Max Offset
(1),
Max Offset
(2)
—Preliminary
(2)
(Part 2 of 2)—Preliminary
2.398
2.406
0.869
1.407
0.825
1.41
Slow Corner
Slow Corner
C7
C7
2.526
2.563
0.933
1.562
0.886
1.566
Cyclone IV Device Handbook,
C8
C8
2.443
2.450
0.884
1.421
0.839
1.424
I7
I7
Volume 3
Unit
Unit
ns
ns
ns
ns
ns
ns
1–37