EP4CGX110DF31I7N Altera Corporation, EP4CGX110DF31I7N Datasheet - Page 31
EP4CGX110DF31I7N
Manufacturer Part Number
EP4CGX110DF31I7N
Description
IC CYCLONE IV FPGA 110K 896FBGA
Manufacturer
Altera Corporation
Series
CYCLONE® IV GXr
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CGX110DF31I7N
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5621760
Number Of I /o
475
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices
Table 1–34. True LVDS Transmitter Timing Specifications for Cyclone IV Devices
November 2011 Altera Corporation
t
Notes to
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
(3) t
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
f
clock
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Cyclone IV E—true LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6.
(2) t
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
LOCK
HSCLK
DUTY
LOCK
Symbol
Symbol
the output pin of all I/O banks.
Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Cyclone IV GX—true LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6.
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
LOCK
LOCK
(3)
(2)
(input
Table
Table
is the time required for the PLL to lock from the end-of-device configuration.
is the time required for the PLL to lock from the end-of-device configuration.
1–33:
1–34:
Modes
×10
×10
Modes
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
Min Typ Max Min Typ
—
C6
Max
420
420
420
420
420
420
840
840
840
840
840
420
200
500
—
55
C6
1
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C7, I7
—
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
55
C7, I7
1
—
Max
Min
100
1
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C8, A7
Min Typ
—
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
200
550
55
1
C8, A7
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
(1),
(1), (2),
Max
C8L, I8L
1
(3)
—Preliminary
Max
(4)
320
320
320
320
320
362
640
640
640
640
640
362
200
600
Min Typ
55
1
—
(Part 2 of 2)—Preliminary
C8L, I8L
—
Cyclone IV Device Handbook,
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C9L
Max
1
Max
250
250
250
250
250
265
500
500
500
500
500
265
200
700
55
1
Min Typ
—
Volume 3
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
MHz
MHz
MHz
MHz
MHz
MHz
ms
ps
ps
%
—
C9L
1–31
Max
1
Unit
ms