EP2AGX65CU17C6N Altera Corporation, EP2AGX65CU17C6N Datasheet - Page 78

• Manufacturer Part Number: EP2AGX65CU17C6N
• Description: IC ARRIA II GX FPGA 65K 358UBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX65CU17C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5371904
• Number Of I /o: 156
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 358-UBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

1–70
Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Clock period jitter
Cycle-to-cycle period
jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
(3) The memory output clock jitter stated in
clock network.
Parameter
Table
1–62:
Table 1–60
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices
Table 1–61
Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices
Table 1–62
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Network
Number of DQS Delay Buffer
Number of DQS Delay Buffer
Global
Global
Global
Clock
buffers in a C4 speed grade is ± 78 ps or ± 39 ps.
buffers in a 3 speed grade is ± 84 ps or ± 42 ps.
Table
Table
(Note 1)
(Note 1)
lists the DQS phase shift error for Arria II GX devices.
lists the DQS phase shift error for Arria II GZ devices.
lists the memory output clock jitter specifications for Arria II GX devices.
1–60:
1–61:
Table 1–62
Symbol
1
2
3
4
t
t
1
2
3
4
t
JIT(duty)
JIT(per)
JIT(cc)
is applicable when an input jitter of 30 ps is applied.
-100
-200
-100
Min
–4
Max
100
200
100
104
C4
26
52
78
112
–3
28
56
84
-125
-250
-125
Min
(Note
I3, C5, I5
Chapter 1: Device Datasheet for Arria II Devices
–5
120
30
60
90
Max
1), (2),
125
250
125
December 2011 Altera Corporation
120
–4
30
60
90
(3)
-125
-250
-125
Min
DQS_PSERR
DQS_PSERR
108
144
Switching Characteristics
C6
36
72
–6
) for Arria II GX
) for Arria II GZ
Max
125
250
125
Unit
ps
ps
ps
ps
Unit
ps
ps
ps
ps
Unit
ps
ps
ps