EP2AGX125EF35I3N Altera Corporation, EP2AGX125EF35I3N Datasheet - Page 63

• Manufacturer Part Number: EP2AGX125EF35I3N
• Description: IC ARRIA II GX 125K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX125EF35I3N

• Number Of Logic Elements/cells: 118143
• Number Of Labs/clbs: 4964
• Total Ram Bits: 8315904
• Number Of I /o: 452
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
December 2011 Altera Corporation
t
OUTJITTER_
PERIOD_
DEDCLK
Notes to
(1) f
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
(4) F
(5) This specification is limited by the lower of the two: I/O f
(6) Peak-to-peak jitter with a probability level of 10
(7) The cascaded PLL specification is only applicable with the following condition:
f
f
f
t
f
f
t
t
t
t
f
t
CASC_
(6)
IN
INPFD
VCO
EINDUTY
OUT
OUT_EXT
OUTDUTY
FCOMP
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
Symbol
Symbol
,
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
less than 200 ps.
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in
a. Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7)
IN
REF
is limited by the I/O f
Table
is fIN/N when N = 1.
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT  100 MHz)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT  100 MHz)
1–44:
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–3 speed grade)
Output frequency for internal global or regional clock
(–4 speed grade)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
Time required to reconfigure scan chain
Time required to reconfigure phase shift
scanclk frequency
Time required to lock from end-of-device configuration or
de-assertion of areset
Table 1–45
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
MAX
.
lists the PLL specifications for Arria II GZ devices when operating in both
Description
Parameter
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
Table 1–62 on page
MAX
or f
OUT
of the PLL.
1–70.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
600
600
40
—
—
—
—
45
—
—
—
—
—
Min
5
5
5
—
—
Typ
3.5
—
—
—
—
—
—
—
—
—
—
50
—
—
—
1
Typ
—
—
717
717
700
500
717
717
1,300
1,300
Max
325
100
Max
42.5
60
55
10
—
—
425
1
VCO
(1)
(1)
(2)
(2)
(2)
(2)
specification.
mUI (p-p)
ps (p-p)
scanclk
scanclk
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ms
ns
%
%
1–55