EP4SE360F35C4N Altera Corporation, EP4SE360F35C4N Datasheet - Page 56
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EP4SE360F35C4N
Manufacturer Part Number
EP4SE360F35C4N
Description
IC STRATIX IV FPGA 360K 1152FBGA
Manufacturer
Altera Corporation
Series
STRATIX® IV Er
Datasheet
1.EP4SGX70DF29C4N.pdf
(80 pages)
Specifications of EP4SE360F35C4N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
23105536
Number Of I /o
744
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE360F35C4N
Manufacturer:
ALTERA
Quantity:
745
Part Number:
EP4SE360F35C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–48
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)—Preliminary
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
t
t
t
t
f
Notes to
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
(3) This specification is limited by the lower of the two: I/O F
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
(5) F
(6) Peak-to-peak jitter with a probability level of 10
(7) The cascaded PLL specification is only applicable with the following condition:
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in
OUTCCJ_DC
OUTPJ_IO
(9)
OUTCCJ_IO
(9)
CASC_OUTPJ_DC
(6),
DRIFT
Symbol
standard.
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
than 120 ps.
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in
A. Upstream PLL: 0.59Mhz
B. Downstream PLL: Downstream PLL BW > 2 MHz
page
REF
(7)
Table
is fIN/N when N = 1.
1–60.
(6),
(6),
(6)
1–34:
Cycle to Cycle Jitter for dedicated clock output
(F
Cycle to Cycle Jitter for dedicated clock output
(F
Period Jitter for clock output on regular I/O
(F
Period Jitter for clock output on regular I/O
(F
Cycle to Cycle Jitter for clock output on regular I/O
(F
Cycle to Cycle Jitter for clock output on regular I/O
(F
Period Jitter for dedicated clock output in cascaded PLLs
(F
Period Jitter for dedicated clock output in cascaded PLLs
(F
Frequency drift after PFDENA is disabled for duration of
100 us
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
≥ 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100MHz)
≥100MHz)
Upstream PLL BW < 1 MHz
Parameter
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
Table 1–50 on page
MAX
or F
OUT
of the PLL.
1–61.
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Min
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
December 2011 Altera Corporation
Max
17.5
175
600
600
250
±10
60
60
25
Switching Characteristics
VCO
Table 1–48 on
specification.
mUI (p-p)
mUI (p-p)
mUI (p-p)
mUI (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
Unit
%