EP4SE360F35C3 Altera Corporation, EP4SE360F35C3 Datasheet - Page 69
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EP4SE360F35C3
Manufacturer Part Number
EP4SE360F35C3
Description
IC STRATIX IV FPGA 360K 1152FBGA
Manufacturer
Altera Corporation
Series
STRATIX® IV Er
Datasheet
1.EP4SGX70DF29C4N.pdf
(80 pages)
Specifications of EP4SE360F35C3
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
23105536
Number Of I /o
744
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE360F35C3N
Manufacturer:
ALTERA
Quantity:
748
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
I/O Timing
December 2011 Altera Corporation
f
Figure 1–7
Figure 1–7. Timing Diagram for the oe and dyn_term_ctrl Signals
Duty Cycle Distortion (DCD) Specifications
Table 1–50
Table 1–50. Worst-Case DCD on Stratix IV I/O Pins
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O Timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
The Excel-based I/O Timing spreadsheet is downloadable from the
Stratix IV Devices
Output Duty Cycle
dyn_term_ctrl
Symbol
shows the timing diagram for the oe and dyn_term_ctrl signals.
lists the worst-case DCD for Stratix IV devices.
R
oe
X
webpage.
T
Tristate
RS_RT
Min
45
Speed Grade
–2/–2×
Max
55
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Min
Speed Grade
45
T
–3
X
Max
55
Min
Speed Grade
45
–4
Max
55
Literature:
T
Tristate
RS_RT
Unit
%
R
X
1–61