EP4S100G3F45I1N Altera Corporation, EP4S100G3F45I1N Datasheet - Page 2

• Manufacturer Part Number: EP4S100G3F45I1N
• Description: IC STRATIX IV FPGA 290K 1932FBGA
• Manufacturer: Altera Corporation
• Series: STRATIX® IV GTr

Specifications of EP4S100G3F45I1N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17661952
• Number Of I /o: 781
• Number Of Gates: -
• Voltage - Supply: 0.92 V ~ 0.98 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1932-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

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Feature Summary
Stratix IV Device Handbook Volume 1
The following list summarizes the Stratix IV device family features:
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Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices
supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE),
Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI,
Fibre Channel, SFI-5, and Interlaken
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
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Programmable transmitter pre-emphasis and receiver equalization circuitry to
compensate for frequency-dependent losses in the physical medium
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps and 135 mW at 6.375 Gbps per channel
72,600 to 813,050 equivalent LEs per device
7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block
sizes to implement true dual-port memory and FIFO buffers
High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit,
12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery
clocks (PCLK) per device
Programmable power technology that minimizes power while maximizing device
performance
Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide
range of single-ended and differential I/O standards
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic
phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
Support for source-synchronous bus standards, including SGMII, GbE, SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Pinouts for Stratix IV E devices designed to allow migration of designs from
Stratix III to Stratix IV E with minimal PCB impact
For more information, refer to the
IP Compiler for PCI Express User
Chapter 1: Overview for the Stratix IV Device Family
June 2011 Altera Corporation
Feature Summary
Guide.