EP2AGX125DF25I3N Altera Corporation, EP2AGX125DF25I3N Datasheet - Page 61
![no-image](/images/manufacturer_photos/0/0/41/altera_corporation_sml.jpg)
EP2AGX125DF25I3N
Manufacturer Part Number
EP2AGX125DF25I3N
Description
IC ARRIA II GX FPGA 125K 572FBGA
Manufacturer
Altera Corporation
Series
Arria II GXr
Datasheet
1.EP2AGX95EF35C5N.pdf
(90 pages)
Specifications of EP2AGX125DF25I3N
Number Of Logic Elements/cells
118143
Number Of Labs/clbs
4964
Total Ram Bits
8315904
Number Of I /o
260
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
572-FBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
December 2011 Altera Corporation
f
f
f
f
f
t
IN
INPFD
VCO
INDUTY
EINDUTY
INCCJ
(4)
Symbol
(3),
Core Performance Specifications for the Arria II Device Family
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
Input frequency to the PFD
PLL VCO operating Range
Input clock duty cycle
External feedback clock input duty cycle
Input clock cycle-to-cycle jitter (Frequency 100 MHz)
Input clock cycle-to-cycle jitter (Frequency 100 MHz)
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42
Table 1–42. Clock Tree Performance for Arria II GX Devices
Table 1–43
Table 1–43. Clock Tree Performance for Arria II GZ Devices
PLL Specifications
Table 1–44
GCLK and RCLK
GCLK and RCLK
Clock Network
Clock Network
PCLK
PCLK
lists the clock tree specifications for Arria II GX devices.
lists the clock tree specifications for Arria II GZ devices.
lists the PLL specifications for Arria II GX devices.
Description
(2)
I3, C4
500
420
–C3 and –I3
700
500
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Performance
Performance
C5,I5
500
350
Min
600
40
40
—
—
5
5
5
5
–C4 and –I4
Typ
—
—
—
—
—
—
—
—
—
500
450
400
280
C6
670
622
500
1,400
±750
Max
0.15
325
60
60
(1)
(1)
(1)
UI (p–p)
ps (p–p)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
MHz
MHz
Unit
%
%
1–53