STM32F051K6 STMicroelectronics, STM32F051K6 Datasheet - Page 18

• Manufacturer Part Number: STM32F051K6
• Description: Entry-level ARM Cortex-M0 MCU with 32 Kbytes Flash, 48 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F051K6

• Voltage Range: 2.0 V to 3.6 V
• Conversion Range: 0 to 3.6V
• Systick Timer: 24-bit downcounter

Functional overview
3.14
18/22
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interfaces can be served by the DMA controller.
Refer to
Table 5.
1. X = supported.
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. The USART1 supports also SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a
clock domain independent from the CPU clock, allowing the USART1 to wake up the MCU
from Stop mode.
The USART interfaces can be served by the DMA controller.Serial peripheral interface
(SPI).
Refer to
7-bit addressing mode
10-bit addressing mode
Standard mode
Fast mode
Fast Mode Plus with 20mA output drive I/Os
Independent clock
SMBus
Wakeup from STOP
Table 5
Table 6
(up to 400 kbit/s)
STM32F051xx I
for the differences between I2C1 and I2C2.
for the differences between USART1 and USART2.
(up to 100 kbit/s)
I2C features
2
Doc ID 018746 Rev 2
C implementation
(1)
(up to 1 Mbit/s)
I2C1
X
X
X
X
X
X
X
X
STM32F051x
I2C2
X
X
X
X