STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 127
STM32F417IE
Manufacturer Part Number
STM32F417IE
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F415ZG.pdf
(168 pages)
Specifications of STM32F417IE
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F417IEH6
Manufacturer:
ST
Quantity:
20 000
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STM32F415xx, STM32F417xx
Figure 51. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
5.3.25
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
FSMC characteristics
Asynchronous waveforms and timings
Figure 52
Table 74
with the following FSMC configuration:
●
●
●
●
In all timing tables, the
AddressSetupTime = 1
AddressHoldTime = 0x1
DataSetupTime = 0x1
BusTurnAroundDuration = 0x0
provide the corresponding timings. The results shown in these tables are obtained
through
Buffered/Non-buffered DAC
Figure 55
12-bit
digital to
analog
converter
T
HCLK
represent asynchronous waveforms and
is the HCLK clock period.
Doc ID 022063 Rev 2
Buffer(1)
DACx_OUT
C
R
LOAD
LOAD
Electrical characteristics
Table 71
ai17157
through
127/168
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