STM32F415VG STMicroelectronics, STM32F415VG Datasheet - Page 97

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STM32F415VG

Manufacturer Part Number
STM32F415VG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, HW crypto
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F415VG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F415VGT6
Manufacturer:
ST
0
Part Number:
STM32F415VGT6
0
STM32F415xx, STM32F417xx
A device reset allows normal operations to be resumed.
The test results are given in
defined in application note AN1709.
Table 39.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
V
V
Symbol
FESD
EFTB
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
Fast transient voltage burst limits to be
applied through 100 pF on V
pins to induce a functional disturbance
EMS characteristics
Parameter
Table
Doc ID 022063 Rev 2
39. They are based on the EMS levels and classes
DD
and V
SS
V
f
IEC 61000-4-2
V
f
IEC 61000-4-2
HCLK
HCLK
DD
DD
= 3.3 V, LQFP176, T
= 3.3 V, LQFP176, T
= 168 MHz, conforms to
= 168 MHz, conforms to
Conditions
Electrical characteristics
A
A
= +25 °C,
= +25 °C,
Level/
Class
97/168
2B
4A

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