STM32F217IE STMicroelectronics, STM32F217IE Datasheet - Page 22
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STM32F217IE
Manufacturer Part Number
STM32F217IE
Description
High-performance ARM Cortex-M3 MCU with 512 Kbytes Flash, 120 MHz CPU, ART Accelerator, Ethernet, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F215ZG.pdf
(168 pages)
Specifications of STM32F217IE
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
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Description
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Regulator ON
The regulator ON modes are activated by default on LQFP packages. On UFBGA176
package, they are activated by connecting REGOFF to V
V
There are three regulator ON modes:
●
●
●
Regulator OFF
●
Figure 7.
1. This figure is valid both whatever the internal reset mode (ON or OFF).
DD
minimum value is 1.8 V.
MR is used in nominal regulation mode (Run)
LPR is used in Stop mode
Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF/internal reset ON
On UFBGA176 package, REGOFF must be connected to V
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
V
between power domains.
If the time for V
reach 1.8 V, then PA0 should be connected to the NRST pin (see
Otherwise, PA0 should be asserted low externally during POR until V
1.8 V (see
DD
Startup in regulator OFF: slow V
- power-down reset risen after V
should always be higher than V
Figure
CAP_1
CAP_1
8).
and V
Doc ID 17050 Rev 6
and V
CAP_2
CAP_2
pins, in addition to V
to reach 1.08 V is faster than the time for V
CAP_1
CAP_1
DD
slope
and V
/V
CAP_2
SS
CAP_2
.
STM32F215xx, STM32F217xx
DD
stabilization
.
to avoid current injection
DD
.
Figure
DD
reaches
7).
DD
to