STM32F415RG STMicroelectronics, STM32F415RG Datasheet - Page 110
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STM32F415RG
Manufacturer Part Number
STM32F415RG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F415ZG.pdf
(168 pages)
Specifications of STM32F415RG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F415RGT6
Manufacturer:
STMicroelectronics
Quantity:
3 450
Part Number:
STM32F415RGT6
Manufacturer:
ST
Quantity:
20 000
Electrical characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 0
Figure 38. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
110/168
OUT P UT
OUT P UT
NSS input
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
I NPUT
I NPUT
MISO
MISO
MOSI
MOSI
t a(SO)
t SU(NSS)
t a(SO)
t su(SI)
t w(SCKH)
t w(SCKL)
t w(SCKH)
t w(SCKL)
t su(SI)
t SU(NSS)
MS B O UT
t v(SO)
M SB IN
M SB IN
t h(SI)
MS B O UT
t c(SCK)
t v(SO)
Doc ID 022063 Rev 2
t h(SI)
DD
t c(SCK)
and 0.7V
BI T6 OUT
B I T1 IN
t h(SO)
DD
.
B I T1 IN
BI T6 OUT
(1)
t h(SO)
LSB IN
STM32F415xx, STM32F417xx
t r(SCK)
t f(SCK)
LSB OUT
t r(SCK)
t f(SCK)
t h(NSS)
LSB IN
t h(NSS)
LSB OUT
t dis(SO)
t dis(SO)
ai14134c
ai14135