STM8S103K3 STMicroelectronics, STM8S103K3 Datasheet - Page 83

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STM8S103K3

Manufacturer Part Number
STM8S103K3
Description
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S103K3

Program Memory
8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Data Memory
640 bytes true data EEPROM; endurance 300 kcycles
Ram
1 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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STM8S103K3 STM8S103F3 STM8S103F2
10.3.10
Symbol
t
t
C
(1)
(2)
(3)
low time
(4)
the undefined region of the falling edge of SCL
w(STO:ST A)
su(STO)
b
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
f
Data based on standard I
The maximum hold time of the start condition has only to be met if the interface does not stretch the
MASTER
Parameter
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
, must be at least 8 MHz to achieve max fast I
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10-bit ADC characteristics
Subject to general operating conditions for V
Figure 41: Typical application with I
SDA
SCL
I
2
t
C bus
f(SDA)
2
C protocol requirement, not tested in production
t
h(STA)
START
4.7k
t
w(SCLH)
t
r(SDA)
V DD
t
w(SCLL)
4.7k
DocID15441 Rev 7
V DD
t
su(SDA)
Standard mode I
Min
t
r(SCL)
4.0
4.7
100
100
(2)
t
h(SDA)
t
f(SCL)
2
SDA
SCL
DD
C speed (400kHz)
, f
MASTER
STM8S
2
C bus and timing diagram
2
C
Max
, and T
400
(2)
t
su(STA)
A
t
su(STO)
Fast mode I
Min
unless otherwise specified.
Electrical characteristics
0.6
1.3
t
STOP
w(STO:STA)
(2)
REPEATED
START
Max
ai17490
400
START
2
C
(2)
(1)
Unit
μs
pF
83/113

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