STM8AF5268 STMicroelectronics, STM8AF5268 Datasheet - Page 25
STM8AF5268
Manufacturer Part Number
STM8AF5268
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet
1.STM8AF5168.pdf
(106 pages)
Specifications of STM8AF5268
Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
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STM8AF52/62xx, STM8AF51/61xx
5.9.3
5.9.4
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
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Inter integrated circuit (I
The devices covered by this datasheet contain one I
on all the supported packages.
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Maximum speed: 8 Mbit/s or f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
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I
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I
–
–
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
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Status flags:
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Error flags:
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2
2
C master features:
C slave features:
CRC value can be transmitted as last byte in Tx mode
CRC error checking for last received byte
Clock generation
Start and stop generation
Programmable I
Stop bit detection
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
Transmitter/receiver mode flag
End-of-byte transmission flag
I
Arbitration lost condition for master mode
Acknowledgement failure after address/data transmission
Detection of misplaced start or stop condition
Overrun/underrun if clock stretching is disabled
2
C busy flag
2
C address detection
Doc ID 14395 Rev 8
2
C) interface
MASTER
/2 both for master and slave
2
C interface. The interface is available
Product overview
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